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Use Align for TFL::TransientStackAlignment
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, dschuff, jyknight, sdardis, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, fedor.sergeev, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69216 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375398 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -55,12 +55,12 @@ public:
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private:
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StackDirection StackDir;
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Align StackAlignment;
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unsigned TransientStackAlignment;
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Align TransientStackAlignment;
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int LocalAreaOffset;
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bool StackRealignable;
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public:
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TargetFrameLowering(StackDirection D, Align StackAl, int LAO,
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unsigned TransAl = 1, bool StackReal = true)
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Align TransAl = Align::None(), bool StackReal = true)
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: StackDir(D), StackAlignment(StackAl), TransientStackAlignment(TransAl),
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LocalAreaOffset(LAO), StackRealignable(StackReal) {}
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@@ -96,7 +96,7 @@ public:
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/// calls.
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///
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unsigned getTransientStackAlignment() const {
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return TransientStackAlignment;
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return TransientStackAlignment.value();
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}
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/// isStackRealignable - This method returns whether the stack can be
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@@ -10356,7 +10356,7 @@ static bool isKnownPredicateExtendIdiom(ICmpInst::Predicate Pred,
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case ICmpInst::ICMP_UGE:
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std::swap(LHS, RHS);
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LLVM_FALLTHROUGH;
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case ICmpInst::ICMP_ULE: {
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case ICmpInst::ICMP_ULE: {
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// If operand >=s 0 then ZExt == SExt. If operand <s 0 then ZExt <u SExt.
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const SCEVZeroExtendExpr *ZExt = dyn_cast<SCEVZeroExtendExpr>(LHS);
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const SCEVSignExtendExpr *SExt = dyn_cast<SCEVSignExtendExpr>(RHS);
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@@ -21,7 +21,7 @@ namespace llvm {
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class AArch64FrameLowering : public TargetFrameLowering {
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public:
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explicit AArch64FrameLowering()
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: TargetFrameLowering(StackGrowsDown, Align(16), 0, 16,
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: TargetFrameLowering(StackGrowsDown, Align(16), 0, Align(16),
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true /*StackRealignable*/) {}
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void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
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@@ -14,7 +14,7 @@
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using namespace llvm;
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AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, Align StackAl,
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int LAO, unsigned TransAl)
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int LAO, Align TransAl)
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: TargetFrameLowering(D, StackAl, LAO, TransAl) {}
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AMDGPUFrameLowering::~AMDGPUFrameLowering() = default;
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@@ -26,7 +26,7 @@ namespace llvm {
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class AMDGPUFrameLowering : public TargetFrameLowering {
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public:
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AMDGPUFrameLowering(StackDirection D, Align StackAl, int LAO,
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unsigned TransAl = 1);
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Align TransAl = Align::None());
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~AMDGPUFrameLowering() override;
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/// \returns The number of 32-bit sub-registers that are used when storing
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@@ -16,7 +16,7 @@ namespace llvm {
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class R600FrameLowering : public AMDGPUFrameLowering {
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public:
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R600FrameLowering(StackDirection D, Align StackAl, int LAO,
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unsigned TransAl = 1)
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Align TransAl = Align::None())
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: AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
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~R600FrameLowering() override;
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@@ -21,7 +21,7 @@ class GCNSubtarget;
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class SIFrameLowering final : public AMDGPUFrameLowering {
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public:
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SIFrameLowering(StackDirection D, Align StackAl, int LAO,
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unsigned TransAl = 1)
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Align TransAl = Align::None())
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: AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
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~SIFrameLowering() override = default;
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@@ -76,7 +76,7 @@ skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
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unsigned NumAlignedDPRCS2Regs);
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ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
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: TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
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: TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, Align(4)),
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STI(sti) {}
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bool ARMFrameLowering::keepFramePointer(const MachineFunction &MF) const {
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@@ -30,7 +30,7 @@ class TargetRegisterClass;
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class HexagonFrameLowering : public TargetFrameLowering {
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public:
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explicit HexagonFrameLowering()
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: TargetFrameLowering(StackGrowsDown, Align(8), 0, 1, true) {}
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: TargetFrameLowering(StackGrowsDown, Align(8), 0, Align::None(), true) {}
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// All of the prolog/epilog functionality, including saving and restoring
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// callee-saved registers is handled in emitPrologue. This is to have the
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@@ -23,7 +23,7 @@ protected:
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public:
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explicit MSP430FrameLowering()
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(2), -2,
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2) {}
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Align(2)) {}
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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@@ -25,8 +25,8 @@ protected:
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public:
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explicit MipsFrameLowering(const MipsSubtarget &sti, Align Alignment)
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: TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment.value()),
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STI(sti) {}
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: TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {
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}
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static const MipsFrameLowering *create(const MipsSubtarget &ST);
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@@ -35,7 +35,7 @@ DisableLeafProc("disable-sparc-leaf-proc",
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SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
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ST.is64Bit() ? Align(16) : Align(8), 0,
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ST.is64Bit() ? 16 : 8) {}
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ST.is64Bit() ? Align(16) : Align(8)) {}
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void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
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MachineBasicBlock &MBB,
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@@ -47,7 +47,7 @@ static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
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SystemZFrameLowering::SystemZFrameLowering()
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(8),
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-SystemZMC::CallFrameSize, 8,
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-SystemZMC::CallFrameSize, Align(8),
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false /* StackRealignable */) {
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// Create a mapping from register number to save slot offset.
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RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
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@@ -31,7 +31,7 @@ public:
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WebAssemblyFrameLowering()
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: TargetFrameLowering(StackGrowsDown, /*StackAlignment=*/Align(16),
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/*LocalAreaOffset=*/0,
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/*TransientStackAlignment=*/16,
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/*TransientStackAlignment=*/Align(16),
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/*StackRealignable=*/true) {}
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MachineBasicBlock::iterator
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