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Support for the special case of a vector with the canonical form:

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vector_shuffle v1, v2, <2, 6, 3, 7>

I.e.

         vector_shuffle v, undef, <2, 2, 3, 3>

MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36403 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2007-04-24 21:16:55 +00:00
parent 95b3955034
commit 2f9bb1a0a4
2 changed files with 35 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
lib/Target/X86/X86ISelLowering.cpp
View File

@ -379,6 +379,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
} }
if (Subtarget->hasSSE1()) { if (Subtarget->hasSSE1()) {
@ -1776,7 +1778,7 @@ bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
assert(N->getOpcode() == ISD::BUILD_VECTOR); assert(N->getOpcode() == ISD::BUILD_VECTOR);
unsigned NumElems = N->getNumOperands(); unsigned NumElems = N->getNumOperands();
if (NumElems != 4 && NumElems != 8 && NumElems != 16) if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
return false; return false;
for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
@ -1792,6 +1794,29 @@ bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
return true; return true;
} }
/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
/// <2, 2, 3, 3>
bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
assert(N->getOpcode() == ISD::BUILD_VECTOR);
unsigned NumElems = N->getNumOperands();
if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
return false;
for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
SDOperand BitI = N->getOperand(i);
SDOperand BitI1 = N->getOperand(i + 1);
if (!isUndefOrEqual(BitI, j))
return false;
if (!isUndefOrEqual(BitI1, j))
return false;
}
return true;
}
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to MOVSS, /// specifies a shuffle of elements that is suitable for input to MOVSS,
/// MOVSD, and MOVD, i.e. setting the lowest element. /// MOVSD, and MOVD, i.e. setting the lowest element.
@ -2432,7 +2457,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
} }
} }
// Let legalizer expand 2-wide build_vector's. // Let legalizer expand 2-wide build_vectors.
if (EVTBits == 64) if (EVTBits == 64)
return SDOperand(); return SDOperand();
@ -2591,6 +2616,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
} }
if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKLMask(PermMask.Val) || X86::isUNPCKLMask(PermMask.Val) ||
X86::isUNPCKHMask(PermMask.Val)) X86::isUNPCKHMask(PermMask.Val))
return Op; return Op;
@ -2619,6 +2645,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
// Commute is back and try unpck* again. // Commute is back and try unpck* again.
Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKLMask(PermMask.Val) || X86::isUNPCKLMask(PermMask.Val) ||
X86::isUNPCKHMask(PermMask.Val)) X86::isUNPCKHMask(PermMask.Val))
return Op; return Op;
@ -4231,6 +4258,7 @@ X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
isPSHUFHW_PSHUFLWMask(Mask.Val) || isPSHUFHW_PSHUFLWMask(Mask.Val) ||
X86::isUNPCKLMask(Mask.Val) || X86::isUNPCKLMask(Mask.Val) ||
X86::isUNPCKL_v_undef_Mask(Mask.Val) || X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
X86::isUNPCKH_v_undef_Mask(Mask.Val) ||
X86::isUNPCKHMask(Mask.Val)); X86::isUNPCKHMask(Mask.Val));
} }

5
lib/Target/X86/X86ISelLowering.h
View File

@ -231,6 +231,11 @@ namespace llvm {
/// <0, 0, 1, 1> /// <0, 0, 1, 1>
bool isUNPCKL_v_undef_Mask(SDNode *N); bool isUNPCKL_v_undef_Mask(SDNode *N);
/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
/// <2, 2, 3, 3>
bool isUNPCKH_v_undef_Mask(SDNode *N);
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to MOVSS, /// specifies a shuffle of elements that is suitable for input to MOVSS,
/// MOVSD, and MOVD, i.e. setting the lowest element. /// MOVSD, and MOVD, i.e. setting the lowest element.