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Allow vector shifts (shl,lshr,ashr) on SPU.
There was a previous implementation with patterns that would have matched e.g. shl <v4i32> <i32>, but this is not valid LLVM IR so they never were selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila
parent
7f5de8b4c6
commit
31cbac1cfe
@ -2015,9 +2015,9 @@ class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
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RotShiftVec, pattern>;
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class SHLHVecInst<ValueType vectype>:
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SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
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SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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[(set (vectype VECREG:$rT),
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(SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
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(SPUvec_shl (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
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multiclass ShiftLeftHalfword
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{
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@ -2065,9 +2065,9 @@ class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
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multiclass ShiftLeftWord
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{
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def v4i32:
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SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
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SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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[(set (v4i32 VECREG:$rT),
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(SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
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(SPUvec_shl (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
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def r32:
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SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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[(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
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@ -2513,19 +2513,11 @@ class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
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RotShiftVec, pattern>;
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def ROTHMv8i16:
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ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
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ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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[/* see patterns below - $rB must be negated */]>;
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def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
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(ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
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def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
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(ROTHMv8i16 VECREG:$rA,
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(SFIr32 (XSHWr16 R16C:$rB), 0))>;
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def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
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(ROTHMv8i16 VECREG:$rA,
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(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
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def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
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(ROTHMv8i16 VECREG:$rA, (SFHIvec VECREG:$rB, 0))>;
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// ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
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// Note: This instruction doesn't match a pattern because rB must be negated
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@ -2586,19 +2578,11 @@ class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
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RotShiftVec, pattern>;
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def ROTMv4i32:
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ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
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ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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[/* see patterns below - $rB must be negated */]>;
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def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R32C:$rB),
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(ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
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def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R16C:$rB),
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(ROTMv4i32 VECREG:$rA,
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(SFIr32 (XSHWr16 R16C:$rB), 0))>;
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def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R8C:$rB),
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(ROTMv4i32 VECREG:$rA,
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(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
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def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
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(ROTMv4i32 VECREG:$rA, (SFIvec VECREG:$rB, 0))>;
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def ROTMr32:
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ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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@ -2804,20 +2788,12 @@ defm ROTQMBII: RotateMaskQuadByBitsImm;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def ROTMAHv8i16:
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RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
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RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"rotmah\t$rT, $rA, $rB", RotShiftVec,
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[/* see patterns below - $rB must be negated */]>;
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def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R32C:$rB),
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(ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
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def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R16C:$rB),
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(ROTMAHv8i16 VECREG:$rA,
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(SFIr32 (XSHWr16 R16C:$rB), 0))>;
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def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R8C:$rB),
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(ROTMAHv8i16 VECREG:$rA,
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(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
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def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
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(ROTMAHv8i16 VECREG:$rA, (SFHIvec VECREG:$rB, 0))>;
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def ROTMAHr16:
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RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
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@ -2859,20 +2835,12 @@ def : Pat<(sra R16C:$rA, (i8 imm:$val)),
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(ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
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def ROTMAv4i32:
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RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
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RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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"rotma\t$rT, $rA, $rB", RotShiftVec,
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[/* see patterns below - $rB must be negated */]>;
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def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R32C:$rB),
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(ROTMAv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
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def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R16C:$rB),
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(ROTMAv4i32 VECREG:$rA,
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(SFIr32 (XSHWr16 R16C:$rB), 0))>;
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def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R8C:$rB),
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(ROTMAv4i32 VECREG:$rA,
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(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
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def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
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(ROTMAv4i32 VECREG:$rA, (SFIvec (v4i32 VECREG:$rB), 0))>;
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def ROTMAr32:
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RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
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@ -1,7 +1,7 @@
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; RUN: llc < %s -march=cellspu > %t1.s
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; RUN: grep {shlh } %t1.s | count 9
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; RUN: grep {shlh } %t1.s | count 10
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; RUN: grep {shlhi } %t1.s | count 3
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; RUN: grep {shl } %t1.s | count 9
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; RUN: grep {shl } %t1.s | count 11
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; RUN: grep {shli } %t1.s | count 3
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; RUN: grep {xshw } %t1.s | count 5
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; RUN: grep {and } %t1.s | count 14
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@ -14,15 +14,12 @@
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; RUN: grep {rotqbyi } %t1.s | count 1
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; RUN: grep {rotqbii } %t1.s | count 2
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; RUN: grep {rotqbybi } %t1.s | count 1
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; RUN: grep {sfi } %t1.s | count 4
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; RUN: grep {sfi } %t1.s | count 6
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; RUN: cat %t1.s | FileCheck %s
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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; Vector shifts are not currently supported in gcc or llvm assembly. These are
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; not tested.
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; Shift left i16 via register, note that the second operand to shl is promoted
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; to a 32-bit type:
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@ -293,3 +290,55 @@ define i128 @test_lshr_i128( i128 %val ) {
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%rv = lshr i128 %val, 64
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ret i128 %rv
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}
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;Vector shifts
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define <2 x i32> @shl_v2i32(<2 x i32> %val, <2 x i32> %sh) {
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;CHECK: shl
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;CHECK: bi $lr
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%rv = shl <2 x i32> %val, %sh
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ret <2 x i32> %rv
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}
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define <4 x i32> @shl_v4i32(<4 x i32> %val, <4 x i32> %sh) {
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;CHECK: shl
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;CHECK: bi $lr
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%rv = shl <4 x i32> %val, %sh
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ret <4 x i32> %rv
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}
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define <8 x i16> @shl_v8i16(<8 x i16> %val, <8 x i16> %sh) {
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;CHECK: shlh
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;CHECK: bi $lr
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%rv = shl <8 x i16> %val, %sh
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ret <8 x i16> %rv
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}
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define <4 x i32> @lshr_v4i32(<4 x i32> %val, <4 x i32> %sh) {
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;CHECK: rotm
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;CHECK: bi $lr
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%rv = lshr <4 x i32> %val, %sh
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ret <4 x i32> %rv
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}
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define <8 x i16> @lshr_v8i16(<8 x i16> %val, <8 x i16> %sh) {
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;CHECK: sfhi
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;CHECK: rothm
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;CHECK: bi $lr
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%rv = lshr <8 x i16> %val, %sh
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ret <8 x i16> %rv
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}
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define <4 x i32> @ashr_v4i32(<4 x i32> %val, <4 x i32> %sh) {
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;CHECK: rotma
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;CHECK: bi $lr
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%rv = ashr <4 x i32> %val, %sh
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ret <4 x i32> %rv
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}
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define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) {
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;CHECK: sfhi
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;CHECK: rotmah
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;CHECK: bi $lr
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%rv = ashr <8 x i16> %val, %sh
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ret <8 x i16> %rv
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}
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