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[ARM][ARMLoadStoreOptimizer]

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- The load store optimizer is currently merging multiple loads/stores into VLDM/VSTM with more than 16 doubleword registers
- This is an UNPREDICTABLE instruction and shouldn't be done
- It looks like the Limit for how many registers included in a merge got dropped at some point so I am reintroducing it in this patch
- This fixes https://bugs.llvm.org/show_bug.cgi?id=38389

Differential Revision: https://reviews.llvm.org/D52085



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342872 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Luke Cheeseman
2018-09-24 10:42:22 +00:00
parent 2948bf4bf8
commit 33b1a96b81
2 changed files with 54 additions and 0 deletions
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lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+14
View File
@@ -1027,6 +1027,18 @@ void ARMLoadStoreOpt::FormCandidates(const MemOpQueue &MemOps) {
if (AssumeMisalignedLoadStores && !mayCombineMisaligned(*STI, *MI))
CanMergeToLSMulti = CanMergeToLSDouble = false;
// vldm / vstm limit are 32 for S variants, 16 for D variants.
unsigned Limit;
switch (Opcode) {
default:
Limit = UINT_MAX;
break;
case ARM::VLDRD:
case ARM::VSTRD:
Limit = 16;
break;
}
// Merge following instructions where possible.
for (unsigned I = SIndex+1; I < EIndex; ++I, ++Count) {
int NewOffset = MemOps[I].Offset;
@@ -1036,6 +1048,8 @@ void ARMLoadStoreOpt::FormCandidates(const MemOpQueue &MemOps) {
unsigned Reg = MO.getReg();
if (Reg == ARM::SP || Reg == ARM::PC)
break;
if (Count == Limit)
break;
// See if the current load/store may be part of a multi load/store.
unsigned RegNum = MO.isUndef() ? std::numeric_limits<unsigned>::max()
test/CodeGen/ARM/load_store_opt_reg_limit.mir
+40
View File
@@ -0,0 +1,40 @@
# RUN: llc -mtriple=thumbv7--linux-android -verify-machineinstrs -run-pass=arm-ldst-opt %s -o - | FileCheck %s --check-prefix=CHECK-MERGE
#CHECK-MERGE: foo
name: foo
# CHECK-MERGE: VSTMDIA $r4, 14, $noreg, $d15, $d16, $d17, $d18, $d19, $d20, $d21, $d22, $d23, $d24, $d25, $d26, $d27, $d28, $d29, $d30
# CHECK-MERGE-NEXT: VSTRD $d31, $r4, 32, 14, $noreg :: (store 8)
# CHECK-MERGE: VSTMDIA killed $r0, 14, $noreg, $d4, $d5, $d6, $d7, $d8, $d9, $d10, $d11, $d12, $d13, $d14
body: |
bb.0:
VSTRD $d15, $r4, 0, 14, $noreg :: (store 8)
VSTRD $d16, $r4, 2, 14, $noreg :: (store 8)
VSTRD $d17, $r4, 4, 14, $noreg :: (store 8)
VSTRD $d18, $r4, 6, 14, $noreg :: (store 8)
VSTRD $d19, $r4, 8, 14, $noreg :: (store 8)
VSTRD $d20, $r4, 10, 14, $noreg :: (store 8)
VSTRD $d21, $r4, 12, 14, $noreg :: (store 8)
VSTRD $d22, $r4, 14, 14, $noreg :: (store 8)
VSTRD $d23, $r4, 16, 14, $noreg :: (store 8)
VSTRD $d24, $r4, 18, 14, $noreg :: (store 8)
VSTRD $d25, $r4, 20, 14, $noreg :: (store 8)
VSTRD $d26, $r4, 22, 14, $noreg :: (store 8)
VSTRD $d27, $r4, 24, 14, $noreg :: (store 8)
VSTRD $d28, $r4, 26, 14, $noreg :: (store 8)
VSTRD $d29, $r4, 28, 14, $noreg :: (store 8)
VSTRD $d30, $r4, 30, 14, $noreg :: (store 8)
VSTRD $d31, $r4, 32, 14, $noreg :: (store 8)
VSTRD $d0, $r4, 34, 14, $noreg :: (store 8)
VSTRD $d1, $r4, 36, 14, $noreg :: (store 8)
VSTRD $d3, $r4, 38, 14, $noreg :: (store 8)
VSTRD $d2, $r4, 40, 14, $noreg :: (store 8)
VSTRD $d4, $r4, 42, 14, $noreg :: (store 8)
VSTRD $d5, $r4, 44, 14, $noreg :: (store 8)
VSTRD $d6, $r4, 46, 14, $noreg :: (store 8)
VSTRD $d7, $r4, 48, 14, $noreg :: (store 8)
VSTRD $d8, $r4, 50, 14, $noreg :: (store 8)
VSTRD $d9, $r4, 52, 14, $noreg :: (store 8)
VSTRD $d10, $r4, 54, 14, $noreg :: (store 8)
VSTRD $d11, $r4, 56, 14, $noreg :: (store 8)
VSTRD $d12, $r4, 58, 14, $noreg :: (store 8)
VSTRD $d13, $r4, 60, 14, $noreg :: (store 8)
VSTRD $d14, $r4, 62, 14, $noreg :: (store 8)