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[Hexagon] Adding post-increment signed byte loads with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224866 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
21b9b20f36
commit
3c52b7b9f2
@ -610,7 +610,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
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} else if (LoadedVT == MVT::i8) {
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if (TII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib;
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Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::L2_loadrb_pi;
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else
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Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
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} else
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@ -694,7 +694,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
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case Hexagon::POST_LDriuh:
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return isShiftedInt<4,1>(MI->getOperand(3).getImm());
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case Hexagon::POST_LDrib:
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case Hexagon::L2_loadrb_pi:
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case Hexagon::POST_LDriub:
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return isInt<4>(MI->getOperand(3).getImm());
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@ -1363,8 +1363,8 @@ isConditionalLoad (const MachineInstr* MI) const {
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case Hexagon::POST_LDriw_cNotPt :
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case Hexagon::POST_LDrih_cPt :
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case Hexagon::POST_LDrih_cNotPt :
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case Hexagon::POST_LDrib_cPt :
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case Hexagon::POST_LDrib_cNotPt :
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case Hexagon::L2_ploadrbt_pi :
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case Hexagon::L2_ploadrbf_pi :
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case Hexagon::POST_LDriuh_cPt :
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case Hexagon::POST_LDriuh_cNotPt :
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case Hexagon::POST_LDriub_cPt :
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@ -1599,6 +1599,106 @@ def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
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//===----------------------------------------------------------------------===//
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// Post increment load
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Template class for non-predicated post increment loads with immediate offset.
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, addrMode = PostInc in
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class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<4> MajOp >
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: LDInstPI <(outs RC:$dst, IntRegs:$dst2),
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(ins IntRegs:$src1, ImmOp:$offset),
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"$dst = "#mnemonic#"($src1++#$offset)" ,
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[],
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"$src1 = $dst2" > ,
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PredNewRel {
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bits<5> dst;
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bits<5> src1;
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bits<7> offset;
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bits<4> offsetBits;
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string ImmOpStr = !cast<string>(ImmOp);
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let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
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!if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
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!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
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/* s4_0Imm */ offset{3-0})));
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let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
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let IClass = 0b1001;
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let Inst{27-25} = 0b101;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = src1;
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let Inst{13-12} = 0b00;
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let Inst{8-5} = offsetBits;
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let Inst{4-0} = dst;
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}
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//===----------------------------------------------------------------------===//
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// Template class for predicated post increment loads with immediate offset.
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//===----------------------------------------------------------------------===//
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let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
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class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<4> MajOp, bit isPredNot, bit isPredNew >
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: LDInst <(outs RC:$dst, IntRegs:$dst2),
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(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
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!if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#"$dst = "#mnemonic#"($src2++#$offset)",
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[] ,
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"$src2 = $dst2" > ,
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PredNewRel {
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bits<5> dst;
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bits<2> src1;
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bits<5> src2;
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bits<7> offset;
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bits<4> offsetBits;
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let isPredicatedNew = isPredNew;
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let isPredicatedFalse = isPredNot;
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string ImmOpStr = !cast<string>(ImmOp);
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let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
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!if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
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!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
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/* s4_0Imm */ offset{3-0})));
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let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
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let IClass = 0b1001;
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let Inst{27-25} = 0b101;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = src2;
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let Inst{13} = 0b1;
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let Inst{12} = isPredNew;
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let Inst{11} = isPredNot;
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let Inst{10-9} = src1;
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let Inst{8-5} = offsetBits;
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let Inst{4-0} = dst;
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}
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//===----------------------------------------------------------------------===//
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// Multiclass for post increment loads with immediate offset.
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//===----------------------------------------------------------------------===//
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multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
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Operand ImmOp, bits<4> MajOp> {
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let BaseOpcode = "POST_"#BaseOp in {
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let isPredicable = 1 in
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def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
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// Predicated
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def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
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def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
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// Predicated new
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def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
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def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
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}
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}
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// post increment byte loads with immediate offset
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let accessSize = ByteAccess, isCodeGenOnly = 0 in {
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defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
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}
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multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
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bit isNot, bit isPredNew> {
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@ -1621,7 +1721,7 @@ multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
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}
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}
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multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
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multiclass LD_PostInc2<string mnemonic, string BaseOp, RegisterClass RC,
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Operand ImmOp> {
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let BaseOpcode = "POST_"#BaseOp in {
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@ -1640,17 +1740,15 @@ multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
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}
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let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
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defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
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defm POST_LDriub : LD_PostInc2<"memub", "LDriub", IntRegs, s4_0Imm>,
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PredNewRel;
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defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
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defm POST_LDrih : LD_PostInc2<"memh", "LDrih", IntRegs, s4_1Imm>,
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PredNewRel;
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defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
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defm POST_LDriuh : LD_PostInc2<"memuh", "LDriuh", IntRegs, s4_1Imm>,
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PredNewRel;
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defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
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defm POST_LDriw : LD_PostInc2<"memw", "LDriw", IntRegs, s4_2Imm>,
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PredNewRel;
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defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
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PredNewRel;
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defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
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defm POST_LDrid : LD_PostInc2<"memd", "LDrid", DoubleRegs, s4_3Imm>,
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PredNewRel;
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}
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@ -10,6 +10,7 @@
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0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x47
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21 + #24)
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0xf1 0xc3 0x15 0x91
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# CHECK: r17 = memb(r21 + #31)
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0x91 0xdd 0x15 0x41
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@ -22,10 +23,14 @@
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0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44)
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0xf1 0xc3 0x55 0x91
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# CHECK: r17 = memh(r21 + #62)
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0xf1 0xc3 0x35 0x91
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# CHECK: r17 = memub(r21 + #31)
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0xb1 0xc0 0x15 0x9b
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# CHECK: r17 = memb(r21++#5)
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0xf1 0xdb 0x35 0x41
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# CHECK: if (p3) r17 = memub(r21 + #31)
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0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43
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@ -36,6 +41,17 @@
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0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x47
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memub(r21 + #31)
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0xb1 0xe6 0x15 0x9b
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# CHECK: if (p3) r17 = memb(r21++#5)
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0xb1 0xee 0x15 0x9b
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# CHECK: if (!p3) r17 = memb(r21++#5)
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0x03 0x40 0x45 0x85 0xb1 0xf6 0x15 0x9b
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) r17 = memb(r21++#5)
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0x03 0x40 0x45 0x85 0xb1 0xfe 0x15 0x9b
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
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0xb1 0xc2 0x75 0x91
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# CHECK: r17 = memuh(r21 + #42)
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0xb1 0xda 0x75 0x41
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@ -48,6 +64,7 @@
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0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42)
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0xb1 0xc2 0x95 0x91
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# CHECK: r17 = memw(r21 + #84)
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0xb1 0xda 0x95 0x41
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