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[AArch64] Adding support for PMMIR_EL1 register

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Summary:
The PMMIR_EL1 register is present in Armv8.4 with PMU extension.
This patch adds support for it.

Reviewers: t.p.northover, dnsampaio

Reviewed By: dnsampaio

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375228 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Victor Campos
2019-10-18 12:40:29 +00:00
parent 77a2562985
commit 3e5185e268
6 changed files with 45 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/Target/AArch64/AArch64.td
+5 -1
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@@ -285,6 +285,10 @@ def FeatureSEL2 : SubtargetFeature<
"sel2", "HasSEL2", "true",
"Enable v8.4-A Secure Exception Level 2 extension">;
def FeaturePMU : SubtargetFeature<
"pmu", "HasPMU", "true",
"Enable v8.4-A PMU extension">;
def FeatureTLB_RMI : SubtargetFeature<
"tlb-rmi", "HasTLB_RMI", "true",
"Enable v8.4-A TLB Range and Maintenance Instructions">;
@@ -380,7 +384,7 @@ def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
FeatureFMI, FeatureRCPC_IMMO]>;
def HasV8_5aOps : SubtargetFeature<
lib/Target/AArch64/AArch64InstrInfo.td
+3
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@@ -62,6 +62,9 @@ def HasAM : Predicate<"Subtarget->hasAM()">,
def HasSEL2 : Predicate<"Subtarget->hasSEL2()">,
AssemblerPredicate<"FeatureSEL2", "sel2">;
def HasPMU : Predicate<"Subtarget->hasPMU()">,
AssemblerPredicate<"FeaturePMU", "pmu">;
def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">,
AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">;
lib/Target/AArch64/AArch64Subtarget.h
+2
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@@ -116,6 +116,7 @@ protected:
bool HasTRACEV8_4 = false;
bool HasAM = false;
bool HasSEL2 = false;
bool HasPMU = false;
bool HasTLB_RMI = false;
bool HasFMI = false;
bool HasRCPC_IMMO = false;
@@ -435,6 +436,7 @@ public:
bool hasTRACEV8_4() const { return HasTRACEV8_4; }
bool hasAM() const { return HasAM; }
bool hasSEL2() const { return HasSEL2; }
bool hasPMU() const { return HasPMU; }
bool hasTLB_RMI() const { return HasTLB_RMI; }
bool hasFMI() const { return HasFMI; }
bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
lib/Target/AArch64/AArch64SystemOperands.td
+6
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@@ -1322,6 +1322,12 @@ def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>;
def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;
} // FeatureSEL2
// v8.4a PMU registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeaturePMU} }] in {
def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
} // FeaturePMU
// v8.4a RAS registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureRASv8_4} }] in {
test/MC/AArch64/armv8.4a-pmu.s
+19
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@@ -0,0 +1,19 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s \
// RUN: | FileCheck %s --check-prefix=CHECK
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
//------------------------------------------------------------------------------
// ARMV8.4-A PMU
//------------------------------------------------------------------------------
// Read/Write registers:
msr PMMIR_EL1, x0
mrs x0, PMMIR_EL1
//CHECK: msr PMMIR_EL1, x0 // encoding: [0xc0,0x9e,0x18,0xd5]
//CHECK: mrs x0, PMMIR_EL1 // encoding: [0xc0,0x9e,0x38,0xd5]
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: error: expected readable system register
test/MC/Disassembler/AArch64/armv8.4a-pmu.txt
+10
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@@ -0,0 +1,10 @@
#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s | FileCheck %s --check-prefix=CHECK-NOV84
[0xc0,0x9e,0x18,0xd5]
[0xc0,0x9e,0x38,0xd5]
#CHECK: msr PMMIR_EL1, x0
#CHECK: mrs x0, PMMIR_EL1
#CHECK-NOV84: msr S3_0_C9_C14_6, x0
#CHECK-NOV84: mrs x0, S3_0_C9_C14_6