mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-19 15:13:49 -04:00
[X86] Support LEA64_32r in processInstrForSlow3OpLEA and use INC/DEC when possible.
Move the erasing and iterator updating inside to match the other slow LEA function. I've adapted code from optTwoAddrLEA and basically rebuilt the implementation here. We do lose the kill flags now just like optTwoAddrLEA. This runs late enough in the pipeline that shouldn't really be a problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373877 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
+111
-81
@@ -67,8 +67,8 @@ class FixupLEAPass : public MachineFunctionPass {
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/// - LEA that uses RIP relative addressing mode
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/// - LEA that uses 16-bit addressing mode "
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/// This function currently handles the first 2 cases only.
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MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
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MachineBasicBlock &MBB);
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void processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I,
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MachineBasicBlock &MBB, bool OptIncDec);
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/// Look for LEAs that are really two address LEAs that we might be able to
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/// turn into regular ADD instructions.
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@@ -216,14 +216,10 @@ bool FixupLEAPass::runOnMachineFunction(MachineFunction &MF) {
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if (optTwoAddrLEA(I, MBB, OptIncDec, UseLEAForSP))
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continue;
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if (IsSlowLEA) {
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if (IsSlowLEA)
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processInstructionForSlowLEA(I, MBB);
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} else if (IsSlow3OpsLEA) {
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if (auto *NewMI = processInstrForSlow3OpLEA(*I, MBB)) {
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MBB.erase(I);
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I = NewMI;
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}
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}
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else if (IsSlow3OpsLEA)
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processInstrForSlow3OpLEA(I, MBB, OptIncDec);
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}
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// Second pass for creating LEAs. This may reverse some of the
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@@ -301,18 +297,14 @@ static inline bool isInefficientLEAReg(unsigned Reg) {
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Reg == X86::R13D || Reg == X86::R13;
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}
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static inline bool isRegOperand(const MachineOperand &Op) {
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return Op.isReg() && Op.getReg() != X86::NoRegister;
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}
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/// Returns true if this LEA uses base an index registers, and the base register
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/// is known to be inefficient for the subtarget.
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// TODO: use a variant scheduling class to model the latency profile
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// of LEA instructions, and implement this logic as a scheduling predicate.
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static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
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const MachineOperand &Index) {
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return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
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isRegOperand(Index);
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return Base.isReg() && isInefficientLEAReg(Base.getReg()) && Index.isReg() &&
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Index.getReg() != X86::NoRegister;
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}
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static inline bool hasLEAOffset(const MachineOperand &Offset) {
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@@ -534,112 +526,150 @@ void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
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}
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}
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MachineInstr *
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FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
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MachineBasicBlock &MBB) {
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void FixupLEAPass::processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I,
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MachineBasicBlock &MBB,
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bool OptIncDec) {
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MachineInstr &MI = *I;
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const unsigned LEAOpcode = MI.getOpcode();
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const MachineOperand &Dst = MI.getOperand(0);
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const MachineOperand &Dest = MI.getOperand(0);
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const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
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const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
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const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
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const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
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const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
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if (!(TII->isThreeOperandsLEA(MI) ||
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hasInefficientLEABaseReg(Base, Index)) ||
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if (!(TII->isThreeOperandsLEA(MI) || hasInefficientLEABaseReg(Base, Index)) ||
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!TII->isSafeToClobberEFLAGS(MBB, MI) ||
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Segment.getReg() != X86::NoRegister)
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return nullptr;
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return;
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Register DestReg = Dest.getReg();
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Register BaseReg = Base.getReg();
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Register IndexReg = Index.getReg();
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if (MI.getOpcode() == X86::LEA64_32r) {
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if (BaseReg != 0)
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BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
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if (IndexReg != 0)
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IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
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}
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Register DstR = Dst.getReg();
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Register BaseR = Base.getReg();
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Register IndexR = Index.getReg();
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Register SSDstR =
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(LEAOpcode == X86::LEA64_32r) ? Register(getX86SubSuperRegister(DstR, 64))
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: DstR;
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bool IsScale1 = Scale.getImm() == 1;
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bool IsInefficientBase = isInefficientLEAReg(BaseR);
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bool IsInefficientIndex = isInefficientLEAReg(IndexR);
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bool IsInefficientBase = isInefficientLEAReg(BaseReg);
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bool IsInefficientIndex = isInefficientLEAReg(IndexReg);
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// Skip these cases since it takes more than 2 instructions
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// to replace the LEA instruction.
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if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
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return nullptr;
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if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
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(IsInefficientIndex || !IsScale1))
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return nullptr;
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const DebugLoc DL = MI.getDebugLoc();
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const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
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const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
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if (IsInefficientBase && DestReg == BaseReg && !IsScale1)
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return;
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LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
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LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
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MachineInstr *NewMI = nullptr;
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// First try to replace LEA with one or two (for the 3-op LEA case)
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// add instructions:
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// 1.lea (%base,%index,1), %base => add %index,%base
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// 2.lea (%base,%index,1), %index => add %base,%index
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if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
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const MachineOperand &Src = DstR == BaseR ? Index : Base;
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MachineInstr *NewMI =
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BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
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if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) {
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unsigned NewOpc = getADDrrFromLEA(MI.getOpcode());
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if (DestReg != BaseReg)
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std::swap(BaseReg, IndexReg);
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if (MI.getOpcode() == X86::LEA64_32r) {
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// TODO: Do we need the super register implicit use?
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NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
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.addReg(BaseReg)
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.addReg(IndexReg)
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.addReg(Base.getReg(), RegState::Implicit)
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.addReg(Index.getReg(), RegState::Implicit);
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} else {
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NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
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.addReg(BaseReg)
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.addReg(IndexReg);
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}
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} else if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
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// If the base is inefficient try switching the index and base operands,
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// otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
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// lea offset(%base,%index,scale),%dst =>
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// lea (%base,%index,scale); add offset,%dst
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NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(LEAOpcode))
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.add(Dest)
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.add(IsInefficientBase ? Index : Base)
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.add(Scale)
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.add(IsInefficientBase ? Base : Index)
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.addImm(0)
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.add(Segment);
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LLVM_DEBUG(NewMI->dump(););
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}
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// If either replacement succeeded above, add the offset if needed, then
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// replace the instruction.
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if (NewMI) {
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// Create ADD instruction for the Offset in case of 3-Ops LEA.
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if (hasLEAOffset(Offset)) {
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NewMI = BuildMI(MBB, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
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LLVM_DEBUG(NewMI->dump(););
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if (OptIncDec && Offset.isImm() &&
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(Offset.getImm() == 1 || Offset.getImm() == -1)) {
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unsigned NewOpc =
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getINCDECFromLEA(MI.getOpcode(), Offset.getImm() == 1);
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NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
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.addReg(DestReg);
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LLVM_DEBUG(NewMI->dump(););
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} else {
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unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset);
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NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
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.addReg(DestReg)
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.add(Offset);
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LLVM_DEBUG(NewMI->dump(););
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}
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}
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return NewMI;
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}
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// If the base is inefficient try switching the index and base operands,
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// otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
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// lea offset(%base,%index,scale),%dst =>
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// lea (%base,%index,scale); add offset,%dst
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if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
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MachineInstr *NewMI = BuildMI(MBB, MI, DL, TII->get(LEAOpcode))
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.add(Dst)
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.add(IsInefficientBase ? Index : Base)
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.add(Scale)
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.add(IsInefficientBase ? Base : Index)
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.addImm(0)
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.add(Segment);
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LLVM_DEBUG(NewMI->dump(););
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// Create ADD instruction for the Offset in case of 3-Ops LEA.
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if (hasLEAOffset(Offset)) {
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NewMI = BuildMI(MBB, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
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LLVM_DEBUG(NewMI->dump(););
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}
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return NewMI;
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MBB.erase(I);
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I = NewMI;
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return;
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}
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// Handle the rest of the cases with inefficient base register:
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assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
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assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");
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assert(IsInefficientBase && "efficient base should be handled already!");
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// FIXME: Handle LEA64_32r.
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if (LEAOpcode == X86::LEA64_32r)
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return;
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// lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
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if (IsScale1 && !hasLEAOffset(Offset)) {
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bool BIK = Base.isKill() && BaseR != IndexR;
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TII->copyPhysReg(MBB, MI, DL, DstR, BaseR, BIK);
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bool BIK = Base.isKill() && BaseReg != IndexReg;
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TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);
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LLVM_DEBUG(MI.getPrevNode()->dump(););
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MachineInstr *NewMI =
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BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
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unsigned NewOpc = getADDrrFromLEA(MI.getOpcode());
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NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
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.addReg(DestReg)
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.add(Index);
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LLVM_DEBUG(NewMI->dump(););
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return NewMI;
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return;
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}
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// lea offset(%base,%index,scale), %dst =>
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// lea offset( ,%index,scale), %dst; add %base,%dst
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MachineInstr *NewMI = BuildMI(MBB, MI, DL, TII->get(LEAOpcode))
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.add(Dst)
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.addReg(0)
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.add(Scale)
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.add(Index)
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.add(Offset)
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.add(Segment);
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NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(LEAOpcode))
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.add(Dest)
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.addReg(0)
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.add(Scale)
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.add(Index)
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.add(Offset)
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.add(Segment);
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LLVM_DEBUG(NewMI->dump(););
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NewMI = BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
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unsigned NewOpc = getADDrrFromLEA(MI.getOpcode());
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NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
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.addReg(DestReg)
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.add(Base);
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LLVM_DEBUG(NewMI->dump(););
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return NewMI;
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MBB.erase(I);
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I = NewMI;
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}
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@@ -104,7 +104,7 @@ frameInfo:
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body: |
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bb.0 (%ir-block.0):
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liveins: $eax, $ebp
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; CHECK: $eax = ADD32rr $eax, killed $ebp
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; CHECK: $eax = ADD32rr $eax, $ebp
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; CHECK: $eax = ADD32ri8 $eax, -5
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$eax = LEA32r killed $eax, 1, killed $ebp, -5, $noreg
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@@ -139,7 +139,7 @@ frameInfo:
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body: |
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bb.0 (%ir-block.0):
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liveins: $eax, $ebp
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; CHECK: $ebp = ADD32rr $ebp, killed $eax
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; CHECK: $ebp = ADD32rr $ebp, $eax
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; CHECK: $ebp = ADD32ri8 $ebp, -5
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$ebp = LEA32r killed $ebp, 1, killed $eax, -5, $noreg
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@@ -315,7 +315,7 @@ frameInfo:
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body: |
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bb.0 (%ir-block.0):
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liveins: $eax, $ebp
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; CHECK: $eax = ADD32rr $eax, killed $ebp
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; CHECK: $eax = ADD32rr $eax, $ebp
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; CHECK: $eax = ADD32ri $eax, 129
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$eax = LEA32r killed $eax, 1, killed $ebp, 129, $noreg
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@@ -177,8 +177,8 @@ frameInfo:
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body: |
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bb.0 (%ir-block.0):
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liveins: $rax, $rbp
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; CHECK: $eax = LEA64_32r killed $rax, 1, killed $rbp, 0
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; CHECK: $eax = ADD32ri8 $eax, -5
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; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags, implicit $rax, implicit $rbp
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; CHECK: $eax = ADD32ri8 $eax, -5, implicit-def $eflags
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$eax = LEA64_32r killed $rax, 1, killed $rbp, -5, $noreg
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RETQ $eax
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@@ -212,8 +212,8 @@ frameInfo:
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body: |
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bb.0 (%ir-block.0):
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liveins: $rax, $rbp
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; CHECK: $ebp = LEA64_32r killed $rax, 1, killed $rbp, 0
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; CHECK: $ebp = ADD32ri8 $ebp, -5
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; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags, implicit $rbp, implicit $rax
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; CHECK: $ebp = ADD32ri8 $ebp, -5, implicit-def $eflags
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$ebp = LEA64_32r killed $rbp, 1, killed $rax, -5, $noreg
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RETQ $ebp
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@@ -281,7 +281,7 @@ frameInfo:
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body: |
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bb.0 (%ir-block.0):
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liveins: $rax, $rbp
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; CHECK: $rax = ADD64rr $rax, killed $rbp
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; CHECK: $rax = ADD64rr $rax, $rbp
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; CHECK: $rax = ADD64ri8 $rax, -5
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$rax = LEA64r killed $rax, 1, killed $rbp, -5, $noreg
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@@ -316,7 +316,7 @@ frameInfo:
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body: |
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bb.0 (%ir-block.0):
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liveins: $rax, $rbp
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; CHECK: $rbp = ADD64rr $rbp, killed $rax
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; CHECK: $rbp = ADD64rr $rbp, $rax
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; CHECK: $rbp = ADD64ri8 $rbp, -5
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$rbp = LEA64r killed $rbp, 1, killed $rax, -5, $noreg
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@@ -635,8 +635,8 @@ frameInfo:
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body: |
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bb.0 (%ir-block.0):
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liveins: $rax, $rbp
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; CHECK: $eax = LEA64_32r killed $rax, 1, killed $rbp, 0
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; CHECK: $eax = ADD32ri $eax, 129
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; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags
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; CHECK: $eax = ADD32ri $eax, 129, implicit-def $eflags
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$eax = LEA64_32r killed $rax, 1, killed $rbp, 129, $noreg
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RETQ $eax
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@@ -772,8 +772,8 @@ frameInfo:
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body: |
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bb.0 (%ir-block.0):
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liveins: $rax, $rbp
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; CHECK: $rax = ADD64rr $rax, killed $rbp
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; CHECK: $rax = ADD64ri32 $rax, 129
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; CHECK: $rax = ADD64rr $rax, $rbp, implicit-def $eflags
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; CHECK: $rax = ADD64ri32 $rax, 129, implicit-def $eflags
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$rax = LEA64r killed $rax, 1, killed $rbp, 129, $noreg
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RETQ $eax
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@@ -19,8 +19,8 @@ define i32 @PR28968(i32 %x) {
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; SLOWLEA3-NEXT: xorl %eax, %eax
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; SLOWLEA3-NEXT: cmpl $1, %edi
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; SLOWLEA3-NEXT: sete %al
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; SLOWLEA3-NEXT: leal (%rax,%rax), %eax
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; SLOWLEA3-NEXT: addl $-1, %eax
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; SLOWLEA3-NEXT: addl %eax, %eax
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; SLOWLEA3-NEXT: decl %eax
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; SLOWLEA3-NEXT: retq
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%cmp = icmp eq i32 %x, 1
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%sel = select i1 %cmp, i32 1, i32 -1
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