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ret 0; works, not much else
still lots of uglyness. Maybe calls will come soon. Fixing the return value of things will be necessary to make alpha work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23832 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
9811ea4567
commit
4907d22a90
@ -24,6 +24,7 @@ namespace llvm {
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class MachineCodeEmitter;
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FunctionPass *createAlphaSimpleInstructionSelector(TargetMachine &TM);
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FunctionPass *createAlphaISelDag(TargetMachine &TM);
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FunctionPass *createAlphaCodePrinterPass(std::ostream &OS,
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TargetMachine &TM);
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FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
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@ -21,6 +21,13 @@
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namespace llvm {
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namespace AlphaISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
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};
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}
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class AlphaTargetLowering : public TargetLowering {
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int VarArgsOffset; // What is the offset to the first vaarg
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int VarArgsBase; // What is the base FrameIndex
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@ -17,10 +17,10 @@
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//Floating-point
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//PALcode
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def u8imm : Operand<i8>;
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def s14imm : Operand<i16>;
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def s16imm : Operand<i16>;
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def s21imm : Operand<i32>;
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def u8imm : Operand<i64>;
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def s14imm : Operand<i64>;
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def s16imm : Operand<i64>;
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def s21imm : Operand<i64>;
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def s64imm : Operand<i64>;
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//===----------------------------------------------------------------------===//
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@ -93,8 +93,10 @@ class FBForm<bits<6> opcode, string asmstr>
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}
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//3.3.3
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class OForm<bits<6> opcode, bits<7> fun, string asmstr>
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class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
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: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
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let Pattern = pattern;
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bits<5> Rc;
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bits<5> Ra;
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bits<5> Rb;
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@ -124,8 +126,10 @@ class OcmForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
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}
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class OFormL<bits<6> opcode, bits<7> fun, string asmstr>
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class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
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: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
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let Pattern = pattern;
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bits<5> Rc;
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bits<5> Ra;
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bits<8> LIT;
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@ -12,6 +12,24 @@
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include "AlphaInstrFormats.td"
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//********************
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//Paterns for matching
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//********************
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def immUExt8 : PatLeaf<(imm), [{
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// immUExt8 predicate - True if the immediate fits in a 8-bit zero extended
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// field. Used by instructions like 'addi'.
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return (unsigned long)N->getValue() == (unsigned char)N->getValue();
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}]>;
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def imm2 : PatLeaf<(imm), [{
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// imm2 predicate - True if the immediate is a 2
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return N->getValue() == 2;
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}]>;
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def imm3 : PatLeaf<(imm), [{
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// imm3 predicate - True if the immediate is a 3
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return N->getValue() == 3;
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}]>;
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// //#define FP $15
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// //#define RA $26
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// //#define PV $27
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@ -112,124 +130,172 @@ let isTwoAddress = 1 in {
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"fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
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}
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def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC">; //Add longword
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def ADDLi : OFormL<0x10, 0x00, "addl $RA,$L,$RC">; //Add longword
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def ADDQ : OForm< 0x10, 0x20, "addq $RA,$RB,$RC">; //Add quadword
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def ADDQi : OFormL<0x10, 0x20, "addq $RA,$L,$RC">; //Add quadword
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def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC">; //Architecture mask
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def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC">; //Architecture mask
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def AND : OForm< 0x11, 0x00, "and $RA,$RB,$RC">; //Logical product
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def ANDi : OFormL<0x11, 0x00, "and $RA,$L,$RC">; //Logical product
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def BIC : OForm< 0x11, 0x08, "bic $RA,$RB,$RC">; //Bit clear
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def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC">; //Bit clear
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def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC">; //Logical sum
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def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC">; //Logical sum
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def CTLZ : OForm< 0x1C, 0x32, "CTLZ $RB,$RC">; //Count leading zero
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def CTPOP : OForm< 0x1C, 0x30, "CTPOP $RB,$RC">; //Count population
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def CTTZ : OForm< 0x1C, 0x33, "CTTZ $RB,$RC">; //Count trailing zero
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def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC">; //Logical equivalence
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def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC">; //Logical equivalence
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def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC">; //Extract byte low
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def EXTBLi : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC">; //Extract byte low
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def EXTLH : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC">; //Extract longword high
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def EXTLHi : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC">; //Extract longword high
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def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC">; //Extract longword low
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def EXTLLi : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC">; //Extract longword low
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def EXTQH : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC">; //Extract quadword high
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def EXTQHi : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC">; //Extract quadword high
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def EXTQ : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC">; //Extract quadword low
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def EXTQi : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC">; //Extract quadword low
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def EXTWH : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC">; //Extract word high
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def EXTWHi : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC">; //Extract word high
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def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC">; //Extract word low
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def EXTWLi : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC">; //Extract word low
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def IMPLVER : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC">; //Implementation version
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def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC">; //Implementation version
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def INSBL : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC">; //Insert byte low
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def INSBLi : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC">; //Insert byte low
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def INSLH : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC">; //Insert longword high
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def INSLHi : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC">; //Insert longword high
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def INSLL : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC">; //Insert longword low
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def INSLLi : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC">; //Insert longword low
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def INSQH : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC">; //Insert quadword high
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def INSQHi : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC">; //Insert quadword high
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def INSQL : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC">; //Insert quadword low
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def INSQLi : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC">; //Insert quadword low
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def INSWH : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC">; //Insert word high
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def INSWHi : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC">; //Insert word high
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def INSWL : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC">; //Insert word low
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def INSWLi : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC">; //Insert word low
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def MSKBL : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC">; //Mask byte low
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def MSKBLi : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC">; //Mask byte low
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def MSKLH : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC">; //Mask longword high
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def MSKLHi : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC">; //Mask longword high
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def MSKLL : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC">; //Mask longword low
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def MSKLLi : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC">; //Mask longword low
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def MSKQH : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC">; //Mask quadword high
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def MSKQHi : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC">; //Mask quadword high
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def MSKQL : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC">; //Mask quadword low
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def MSKQLi : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC">; //Mask quadword low
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def MSKWH : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC">; //Mask word high
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def MSKWHi : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC">; //Mask word high
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def MSKWL : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC">; //Mask word low
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def MSKWLi : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC">; //Mask word low
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def MULL : OForm< 0x13, 0x00, "mull $RA,$RB,$RC">; //Multiply longword
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def MULLi : OFormL<0x13, 0x00, "mull $RA,$L,$RC">; //Multiply longword
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def MULQ : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC">; //Multiply quadword
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def MULQi : OFormL<0x13, 0x20, "mulq $RA,$L,$RC">; //Multiply quadword
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def ORNOT : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC">; //Logical sum with complement
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def ORNOTi : OFormL<0x11, 0x28, "ornot $RA,$L,$RC">; //Logical sum with complement
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def S4ADDL : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC">; //Scaled add longword by 4
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def S4ADDLi : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC">; //Scaled add longword by 4
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def S4ADDQ : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC">; //Scaled add quadword by 4
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def S4ADDQi : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC">; //Scaled add quadword by 4
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def S4SUBL : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC">; //Scaled subtract longword by 4
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def S4SUBLi : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC">; //Scaled subtract longword by 4
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def S4SUBQ : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC">; //Scaled subtract quadword by 4
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def S4SUBQi : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC">; //Scaled subtract quadword by 4
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def S8ADDL : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC">; //Scaled add longword by 8
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def S8ADDLi : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC">; //Scaled add longword by 8
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def S8ADDQ : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC">; //Scaled add quadword by 8
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def S8ADDQi : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC">; //Scaled add quadword by 8
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def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC">; //Scaled subtract longword by 8
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def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC">; //Scaled subtract longword by 8
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def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC">; //Scaled subtract quadword by 8
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def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC">; //Scaled subtract quadword by 8
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def SEXTB : OForm< 0x1C, 0x00, "sextb $RB,$RC">; //Sign extend byte
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def SEXTW : OForm< 0x1C, 0x01, "sextw $RB,$RC">; //Sign extend word
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def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC">; //Shift left logical
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def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC">; //Shift left logical
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def SRA : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC">; //Shift right arithmetic
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def SRAi : OFormL<0x12, 0x3C, "sra $RA,$L,$RC">; //Shift right arithmetic
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def SRL : OForm< 0x12, 0x34, "srl $RA,$RB,$RC">; //Shift right logical
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def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
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[(set GPRC:$RC, (sext_inreg (add GPRC:$RA, GPRC:$RB), i32))]>;
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def ADDLi : OFormL<0x10, 0x00, "addl $RA,$L,$RC",
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[(set GPRC:$RC, (sext_inreg (add GPRC:$RA, immUExt8:$L), i32))]>;
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def ADDQ : OForm< 0x10, 0x20, "addq $RA,$RB,$RC",
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[(set GPRC:$RC, (add GPRC:$RA, GPRC:$RB))]>;
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def ADDQi : OFormL<0x10, 0x20, "addq $RA,$L,$RC",
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[(set GPRC:$RC, (add GPRC:$RA, immUExt8:$L))]>;
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//def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC", []>; //Architecture mask
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//def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC", []>; //Architecture mask
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def AND : OForm< 0x11, 0x00, "and $RA,$RB,$RC",
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[(set GPRC:$RC, (and GPRC:$RA, GPRC:$RB))]>;
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def ANDi : OFormL<0x11, 0x00, "and $RA,$L,$RC",
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[(set GPRC:$RC, (and GPRC:$RA, immUExt8:$L))]>;
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def BIC : OForm< 0x11, 0x08, "bic $RA,$RB,$RC",
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[(set GPRC:$RC, (and GPRC:$RA, (not GPRC:$RB)))]>;
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def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC", []>;
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// [(set GPRC:$RC, (and GPRC:$RA, (not immUExt8:$L)))]>; //FIXME?
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def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC",
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[(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))]>;
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def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC",
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[(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))]>;
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def CTLZ : OForm< 0x1C, 0x32, "CTLZ $RB,$RC", []>;
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// [(set GPRC:$RC, (ctlz GPRC:$RB))]>;
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def CTPOP : OForm< 0x1C, 0x30, "CTPOP $RB,$RC", []>; //Count population
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def CTTZ : OForm< 0x1C, 0x33, "CTTZ $RB,$RC", []>; //Count trailing zero
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def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC",
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[(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))]>;
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def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC", []>;
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// [(set GPRC:$RC, (xor GPRC:$RA, (not immUExt8:$L)))]>;
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//def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC", []>; //Extract byte low
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//def EXTBLi : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC", []>; //Extract byte low
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//def EXTLH : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC", []>; //Extract longword high
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//def EXTLHi : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC", []>; //Extract longword high
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//def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC", []>; //Extract longword low
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//def EXTLLi : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC", []>; //Extract longword low
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//def EXTQH : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC", []>; //Extract quadword high
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//def EXTQHi : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC", []>; //Extract quadword high
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//def EXTQ : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC", []>; //Extract quadword low
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//def EXTQi : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC", []>; //Extract quadword low
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//def EXTWH : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC", []>; //Extract word high
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//def EXTWHi : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC", []>; //Extract word high
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//def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC", []>; //Extract word low
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//def EXTWLi : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC", []>; //Extract word low
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//def IMPLVER : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC", []>; //Implementation version
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//def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC", []>; //Implementation version
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//def INSBL : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC", []>; //Insert byte low
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//def INSBLi : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC", []>; //Insert byte low
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//def INSLH : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC", []>; //Insert longword high
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//def INSLHi : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC", []>; //Insert longword high
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//def INSLL : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC", []>; //Insert longword low
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//def INSLLi : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC", []>; //Insert longword low
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//def INSQH : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC", []>; //Insert quadword high
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//def INSQHi : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC", []>; //Insert quadword high
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//def INSQL : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC", []>; //Insert quadword low
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//def INSQLi : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC", []>; //Insert quadword low
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//def INSWH : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC", []>; //Insert word high
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//def INSWHi : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC", []>; //Insert word high
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//def INSWL : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC", []>; //Insert word low
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//def INSWLi : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC", []>; //Insert word low
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//def MSKBL : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC", []>; //Mask byte low
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//def MSKBLi : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC", []>; //Mask byte low
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//def MSKLH : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC", []>; //Mask longword high
|
||||
//def MSKLHi : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC", []>; //Mask longword high
|
||||
//def MSKLL : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC", []>; //Mask longword low
|
||||
//def MSKLLi : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC", []>; //Mask longword low
|
||||
//def MSKQH : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC", []>; //Mask quadword high
|
||||
//def MSKQHi : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC", []>; //Mask quadword high
|
||||
//def MSKQL : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC", []>; //Mask quadword low
|
||||
//def MSKQLi : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC", []>; //Mask quadword low
|
||||
//def MSKWH : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC", []>; //Mask word high
|
||||
//def MSKWHi : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC", []>; //Mask word high
|
||||
//def MSKWL : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC", []>; //Mask word low
|
||||
//def MSKWLi : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC", []>; //Mask word low
|
||||
def MULL : OForm< 0x13, 0x00, "mull $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (mul GPRC:$RA, GPRC:$RB), i32))]>;
|
||||
def MULLi : OFormL<0x13, 0x00, "mull $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (mul GPRC:$RA, immUExt8:$L), i32))]>;
|
||||
def MULQ : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (mul GPRC:$RA, GPRC:$RB))]>;
|
||||
def MULQi : OFormL<0x13, 0x20, "mulq $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (mul GPRC:$RA, immUExt8:$L))]>;
|
||||
def ORNOT : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (or GPRC:$RA, (not GPRC:$RB)))]>;
|
||||
def ORNOTi : OFormL<0x11, 0x28, "ornot $RA,$L,$RC", []>;
|
||||
// [(set GPRC:$RC, (or GPRC:$RA, (not immUExt8:$L)))]>;
|
||||
def S4ADDL : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (add (shl GPRC:$RA, imm2), GPRC:$RB), i32))]>;
|
||||
def S4ADDLi : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (add (shl GPRC:$RA, imm2), immUExt8:$L), i32))]>;
|
||||
def S4ADDQ : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (add (shl GPRC:$RA, imm2), GPRC:$RB))]>;
|
||||
def S4ADDQi : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (add (shl GPRC:$RA, imm2), immUExt8:$L))]>;
|
||||
def S4SUBL : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (sub (shl GPRC:$RA, imm2), GPRC:$RB), i32))]>;
|
||||
def S4SUBLi : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (sub (shl GPRC:$RA, imm2), immUExt8:$L), i32))]>;
|
||||
def S4SUBQ : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sub (shl GPRC:$RA, imm2), GPRC:$RB))]>;
|
||||
def S4SUBQi : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sub (shl GPRC:$RA, imm2), immUExt8:$L))]>;
|
||||
def S8ADDL : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (add (shl GPRC:$RA, imm3), GPRC:$RB), i32))]>;
|
||||
def S8ADDLi : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (add (shl GPRC:$RA, imm3), immUExt8:$L), i32))]>;
|
||||
def S8ADDQ : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (add (shl GPRC:$RA, imm3), GPRC:$RB))]>;
|
||||
def S8ADDQi : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (add (shl GPRC:$RA, imm3), immUExt8:$L))]>;
|
||||
def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (sub (shl GPRC:$RA, imm3), GPRC:$RB), i32))]>;
|
||||
def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (sub (shl GPRC:$RA, imm3), immUExt8:$L), i32))]>;
|
||||
def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sub (shl GPRC:$RA, imm3), GPRC:$RB))]>;
|
||||
def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sub (shl GPRC:$RA, imm3), immUExt8:$L))]>;
|
||||
|
||||
def SRLi : OFormL<0x12, 0x34, "srl $RA,$L,$RC">; //Shift right logical
|
||||
def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC">; //Subtract longword
|
||||
def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC">; //Subtract longword
|
||||
def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC">; //Subtract quadword
|
||||
def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC">; //Subtract quadword
|
||||
def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC">; //Unsigned multiply quadword high
|
||||
def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC">; //Unsigned multiply quadword high
|
||||
def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC">; //Logical difference
|
||||
def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC">; //Logical difference
|
||||
def ZAP : OForm< 0x12, 0x30, "zap $RA,$RB,$RC">; //Zero bytes
|
||||
def ZAPi : OFormL<0x12, 0x30, "zap $RA,$L,$RC">; //Zero bytes
|
||||
def ZAPNOT : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC">; //Zero bytes not
|
||||
def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC">; //Zero bytes not
|
||||
def SEXTB : OForm< 0x1C, 0x00, "sextb $RB,$RC", []>; //Sign extend byte
|
||||
def SEXTW : OForm< 0x1C, 0x01, "sextw $RB,$RC", []>; //Sign extend word
|
||||
|
||||
def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))]>;
|
||||
def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (shl GPRC:$RA, immUExt8:$L))]>;
|
||||
def SRA : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sra GPRC:$RA, GPRC:$RB))]>;
|
||||
def SRAi : OFormL<0x12, 0x3C, "sra $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sra GPRC:$RA, immUExt8:$L))]>;
|
||||
def SRL : OForm< 0x12, 0x34, "srl $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (srl GPRC:$RA, GPRC:$RB))]>;
|
||||
def SRLi : OFormL<0x12, 0x34, "srl $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (srl GPRC:$RA, immUExt8:$L))]>;
|
||||
def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (sub GPRC:$RA, GPRC:$RB), i32))]>;
|
||||
def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sext_inreg (sub GPRC:$RA, immUExt8:$L), i32))]>;
|
||||
def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>;
|
||||
def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (sub GPRC:$RA, immUExt8:$L))]>;
|
||||
def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC", []>; //Unsigned multiply quadword high
|
||||
def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC", []>; //Unsigned multiply quadword high
|
||||
def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC",
|
||||
[(set GPRC:$RC, (xor GPRC:$RA, GPRC:$RB))]>;
|
||||
def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC",
|
||||
[(set GPRC:$RC, (xor GPRC:$RA, immUExt8:$L))]>;
|
||||
def ZAP : OForm< 0x12, 0x30, "zap $RA,$RB,$RC", []>; //Zero bytes
|
||||
def ZAPi : OFormL<0x12, 0x30, "zap $RA,$L,$RC", []>; //Zero bytes
|
||||
def ZAPNOT : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC", []>; //Zero bytes not
|
||||
def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC", []>; //Zero bytes not
|
||||
|
||||
//Comparison, int
|
||||
def CMPBGE : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC">; //Compare byte
|
||||
def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC">; //Compare byte
|
||||
def CMPEQ : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC">; //Compare signed quadword equal
|
||||
def CMPEQi : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC">; //Compare signed quadword equal
|
||||
def CMPLE : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC">; //Compare signed quadword less than or equal
|
||||
def CMPLEi : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC">; //Compare signed quadword less than or equal
|
||||
def CMPLT : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC">; //Compare signed quadword less than
|
||||
def CMPLTi : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC">; //Compare signed quadword less than
|
||||
def CMPULE : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC">; //Compare unsigned quadword less than or equal
|
||||
def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC">; //Compare unsigned quadword less than or equal
|
||||
def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC">; //Compare unsigned quadword less than
|
||||
def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than
|
||||
def CMPBGE : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC", []>; //Compare byte
|
||||
def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC", []>; //Compare byte
|
||||
def CMPEQ : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC", []>; //Compare signed quadword equal
|
||||
def CMPEQi : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC", []>; //Compare signed quadword equal
|
||||
def CMPLE : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC", []>; //Compare signed quadword less than or equal
|
||||
def CMPLEi : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC", []>; //Compare signed quadword less than or equal
|
||||
def CMPLT : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC", []>; //Compare signed quadword less than
|
||||
def CMPLTi : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC", []>; //Compare signed quadword less than
|
||||
def CMPULE : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC", []>; //Compare unsigned quadword less than or equal
|
||||
def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC", []>; //Compare unsigned quadword less than or equal
|
||||
def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC", []>; //Compare unsigned quadword less than
|
||||
def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC", []>; //Compare unsigned quadword less than
|
||||
|
||||
//Comparison, FP
|
||||
def CMPTEQ : FPForm<0x16, 0x0A5, "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal
|
||||
@ -238,24 +304,27 @@ def CMPTLT : FPForm<0x16, 0x0A6, "cmptlt/su $RA,$RB,$RC">; //Compare T_floating
|
||||
def CMPTUN : FPForm<0x16, 0x0A4, "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered
|
||||
|
||||
//There are in the Multimedia extentions, so let's not use them yet
|
||||
def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
|
||||
def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
|
||||
def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
|
||||
def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
|
||||
def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
|
||||
def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
|
||||
def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
|
||||
def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
|
||||
def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
|
||||
def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
|
||||
def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
|
||||
def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
|
||||
def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
|
||||
//def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
|
||||
//def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
|
||||
//def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
|
||||
//def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
|
||||
//def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
|
||||
//def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
|
||||
//def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
|
||||
//def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
|
||||
//def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
|
||||
//def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
|
||||
//def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
|
||||
//def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
|
||||
//def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
|
||||
|
||||
//End operate
|
||||
|
||||
let isReturn = 1, isTerminator = 1 in
|
||||
let isReturn = 1, isTerminator = 1 in
|
||||
def RET : MbrForm< 0x1A, 0x02, (ops GPRC:$RD, GPRC:$RS, s64imm:$DISP), "ret $RD,($RS),$DISP">; //Return from subroutine
|
||||
//DAG Version:
|
||||
let isReturn = 1, isTerminator = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in
|
||||
def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1">; //Return from subroutine
|
||||
|
||||
def JMP : MbrForm< 0x1A, 0x00, (ops GPRC:$RD, GPRC:$RS, GPRC:$DISP), "jmp $RD,($RS),$DISP">; //Jump
|
||||
let isCall = 1,
|
||||
|
||||
@ -314,7 +314,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const {
|
||||
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
||||
assert((MBBI->getOpcode() == Alpha::RET)
|
||||
assert(((MBBI->getOpcode() == Alpha::RET) || (MBBI->getOpcode() == Alpha::RETDAG))
|
||||
&& "Can only insert epilog into returning blocks");
|
||||
|
||||
bool FP = hasFP(MF);
|
||||
|
||||
@ -32,6 +32,9 @@ namespace llvm {
|
||||
cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
|
||||
cl::desc("Enable LSR for Alpha (beta option!)"),
|
||||
cl::Hidden);
|
||||
cl::opt<bool> EnableAlphaDAG("enable-dag-isel-for-alpha",
|
||||
cl::desc("Enable DAG ISEL for Alpha (beta option!)"),
|
||||
cl::Hidden);
|
||||
}
|
||||
|
||||
unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
|
||||
@ -94,7 +97,10 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM,
|
||||
// Make sure that no unreachable blocks are instruction selected.
|
||||
PM.add(createUnreachableBlockEliminationPass());
|
||||
|
||||
PM.add(createAlphaPatternInstructionSelector(*this));
|
||||
if (EnableAlphaDAG)
|
||||
PM.add(createAlphaISelDag(*this));
|
||||
else
|
||||
PM.add(createAlphaPatternInstructionSelector(*this));
|
||||
|
||||
if (PrintMachineCode)
|
||||
PM.add(createMachineFunctionPrinterPass(&std::cerr));
|
||||
|
||||
@ -14,6 +14,6 @@ TARGET = Alpha
|
||||
BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \
|
||||
AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \
|
||||
AlphaGenInstrInfo.inc AlphaGenCodeEmitter.inc \
|
||||
AlphaGenAsmWriter.inc
|
||||
AlphaGenAsmWriter.inc AlphaGenDAGISel.inc
|
||||
|
||||
include $(LEVEL)/Makefile.common
|
||||
|
||||
Loading…
Reference in New Issue
Block a user