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[AArch64]Add support for spilling FPR8/FPR16.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201287 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu 2014-02-13 02:36:58 +00:00
parent 2798b77586
commit 4f2256187c
2 changed files with 38 additions and 0 deletions
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8
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -487,6 +487,10 @@ AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
default:
llvm_unreachable("Unknown size for regclass");
}
} else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
StoreOp = AArch64::LSFP8_STR;
} else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
StoreOp = AArch64::LSFP16_STR;
} else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
RC->hasType(MVT::f128)) {
switch (RC->getSize()) {
@ -553,6 +557,10 @@ AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
default:
llvm_unreachable("Unknown size for regclass");
}
} else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
LoadOp = AArch64::LSFP8_LDR;
} else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
LoadOp = AArch64::LSFP16_LDR;
} else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
RC->hasType(MVT::f128)) {
switch (RC->getSize()) {

30
test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll Normal file
View File

@ -0,0 +1,30 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
; This file tests the spill of FPR8/FPR16. The volatile loads/stores force the
; allocator to keep the value live until it's needed.
%bigtype_v1i8 = type [20 x <1 x i8>]
define void @spill_fpr8(%bigtype_v1i8* %addr) {
; CHECK-LABEL: spill_fpr8:
; CHECK: 1-byte Folded Spill
; CHECK: 1-byte Folded Reload
%val1 = load volatile %bigtype_v1i8* %addr
%val2 = load volatile %bigtype_v1i8* %addr
store volatile %bigtype_v1i8 %val1, %bigtype_v1i8* %addr
store volatile %bigtype_v1i8 %val2, %bigtype_v1i8* %addr
ret void
}
%bigtype_v1i16 = type [20 x <1 x i16>]
define void @spill_fpr16(%bigtype_v1i16* %addr) {
; CHECK-LABEL: spill_fpr16:
; CHECK: 2-byte Folded Spill
; CHECK: 2-byte Folded Reload
%val1 = load volatile %bigtype_v1i16* %addr
%val2 = load volatile %bigtype_v1i16* %addr
store volatile %bigtype_v1i16 %val1, %bigtype_v1i16* %addr
store volatile %bigtype_v1i16 %val2, %bigtype_v1i16* %addr
ret void
}