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[mips] Sign extend i32 return values on MIPS64
Override getTypeForExtReturn so that functions returning an i32 typed value have it sign extended on MIPS64. Also provide patterns to get rid of unneeded sign extensions for arithmetic instructions which implicitly sign extend their results. Differential Revision: https://reviews.llvm.org/D48374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338019 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stefan Maksimovic
@@ -825,6 +825,45 @@ def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>,
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def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>,
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ISA_MIPS3, GPR_64;
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// Patterns used for matching away redundant sign extensions.
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// MIPS32 arithmetic instructions sign extend their result implicitly.
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def : MipsPat<(i64 (sext (i32 (add GPR32:$src, immSExt16:$imm16)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(ADDiu GPR32:$src, immSExt16:$imm16), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (add GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(ADDu GPR32:$src, GPR32:$src2), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(SUBu GPR32:$src, GPR32:$src2), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(MUL GPR32:$src, GPR32:$src2), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(PseudoMFHI ACC64:$src), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (MipsMFLO ACC64:$src)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(PseudoMFLO ACC64:$src), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(SLLV GPR32:$src, GPR32:$src2), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(SRLV GPR32:$src, GPR32:$src2), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
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def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(SRAV GPR32:$src, GPR32:$src2), sub_32)>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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@@ -299,6 +299,21 @@ def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
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(SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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// Patterns used for matching away redundant sign extensions.
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// MIPS32 arithmetic instructions sign extend their result implicitly.
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def : MipsPat<(i64 (sext (i32 (sdiv GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(DIV GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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def : MipsPat<(i64 (sext (i32 (udiv GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(DIVU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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def : MipsPat<(i64 (sext (i32 (srem GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(MOD GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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def : MipsPat<(i64 (sext (i32 (urem GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(MODU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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// Pseudo instructions
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let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
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@@ -3714,6 +3714,13 @@ static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
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true);
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}
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EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
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ISD::NodeType) const {
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bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
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EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32);
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return VT.bitsLT(MinVT) ? MinVT : VT;
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}
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std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
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parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
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const TargetRegisterInfo *TRI =
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@@ -280,6 +280,9 @@ class TargetRegisterClass;
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return MVT::i32;
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}
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EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
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ISD::NodeType) const override;
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bool isCheapToSpeculateCttz() const override;
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bool isCheapToSpeculateCtlz() const override;
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@@ -1,6 +1,4 @@
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
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; We have to XFAIL this temporarily because of the reversion of r229675.
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; XFAIL: *
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; Currently, the following IR assembly generates a KILL instruction between
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; the bitwise-and instruction and the return instruction. We verify that the
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@@ -195,21 +195,18 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
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;
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; MIPS64-LABEL: and_i32:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: and $1, $4, $5
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: sll $2, $1, 0
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; MIPS64-NEXT: and $2, $4, $5
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;
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; MIPS64R2-LABEL: and_i32:
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; MIPS64R2: # %bb.0: # %entry
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; MIPS64R2-NEXT: and $1, $4, $5
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; MIPS64R2-NEXT: jr $ra
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; MIPS64R2-NEXT: sll $2, $1, 0
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; MIPS64R2-NEXT: and $2, $4, $5
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;
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; MIPS64R6-LABEL: and_i32:
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; MIPS64R6: # %bb.0: # %entry
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; MIPS64R6-NEXT: and $1, $4, $5
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; MIPS64R6-NEXT: jr $ra
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; MIPS64R6-NEXT: sll $2, $1, 0
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; MIPS64R6-NEXT: and $2, $4, $5
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;
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; MM32R3-LABEL: and_i32:
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; MM32R3: # %bb.0: # %entry
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@@ -75,7 +75,8 @@ entry:
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; GP32: not $2, $4
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; GP64: not $2, $4
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; GP64: not $1, $4
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; GP64: sll $2, $1, 0
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; MM: not16 $2, $4
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@@ -169,7 +170,8 @@ entry:
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; GP64: or $[[T0:[0-9]+]], $5, $4
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; GP64: sll $[[T1:[0-9]+]], $[[T0]], 0
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; GP64: not $2, $[[T1]]
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; GP64: not $[[T2:[0-9]+]], $[[T1]]
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; GP64: sll $2, $[[T2]], 0
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; MM32: nor $2, $5, $4
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@@ -106,9 +106,8 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
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;
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; GP64-LABEL: or_i32:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: or $1, $4, $5
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; GP64-NEXT: jr $ra
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; GP64-NEXT: sll $2, $1, 0
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; GP64-NEXT: or $2, $4, $5
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;
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; MM32-LABEL: or_i32:
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; MM32: # %bb.0: # %entry
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@@ -284,8 +283,9 @@ define signext i32 @or_i32_4(i32 signext %b) {
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;
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; GP64-LABEL: or_i32_4:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: ori $1, $4, 4
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; GP64-NEXT: jr $ra
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; GP64-NEXT: ori $2, $4, 4
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; GP64-NEXT: sll $2, $1, 0
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;
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; MM32-LABEL: or_i32_4:
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; MM32: # %bb.0: # %entry
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@@ -450,8 +450,9 @@ define signext i32 @or_i32_31(i32 signext %b) {
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;
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; GP64-LABEL: or_i32_31:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: ori $1, $4, 31
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; GP64-NEXT: jr $ra
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; GP64-NEXT: ori $2, $4, 31
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; GP64-NEXT: sll $2, $1, 0
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;
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; MM32-LABEL: or_i32_31:
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; MM32: # %bb.0: # %entry
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@@ -616,8 +617,9 @@ define signext i32 @or_i32_255(i32 signext %b) {
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;
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; GP64-LABEL: or_i32_255:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: ori $1, $4, 255
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; GP64-NEXT: jr $ra
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; GP64-NEXT: ori $2, $4, 255
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; GP64-NEXT: sll $2, $1, 0
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;
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; MM32-LABEL: or_i32_255:
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; MM32: # %bb.0: # %entry
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@@ -786,8 +788,9 @@ define signext i32 @or_i32_32768(i32 signext %b) {
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;
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; GP64-LABEL: or_i32_32768:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: ori $1, $4, 32768
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; GP64-NEXT: jr $ra
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; GP64-NEXT: ori $2, $4, 32768
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; GP64-NEXT: sll $2, $1, 0
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;
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; MM32-LABEL: or_i32_32768:
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; MM32: # %bb.0: # %entry
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@@ -952,8 +955,9 @@ define signext i32 @or_i32_65(i32 signext %b) {
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;
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; GP64-LABEL: or_i32_65:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: ori $1, $4, 65
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; GP64-NEXT: jr $ra
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; GP64-NEXT: ori $2, $4, 65
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; GP64-NEXT: sll $2, $1, 0
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;
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; MM32-LABEL: or_i32_65:
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; MM32: # %bb.0: # %entry
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@@ -1118,8 +1122,9 @@ define signext i32 @or_i32_256(i32 signext %b) {
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;
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; GP64-LABEL: or_i32_256:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: ori $1, $4, 256
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; GP64-NEXT: jr $ra
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; GP64-NEXT: ori $2, $4, 256
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; GP64-NEXT: sll $2, $1, 0
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;
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; MM32-LABEL: or_i32_256:
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; MM32: # %bb.0: # %entry
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@@ -113,16 +113,17 @@ entry:
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; M2-M3: move $5, $6
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; M2-M3: [[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; M3: sll $2, $5, 0
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; CMOV-64:sll $2, $6, 0
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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; SEL: or $[[T3:[0-9]+]], $[[T2]], $[[T1]]
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; SEL-64: sll $2, $[[T3]], 0
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; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
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; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
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@@ -193,21 +193,18 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
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;
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; MIPS64-LABEL: xor_i32:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: xor $1, $4, $5
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: sll $2, $1, 0
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; MIPS64-NEXT: xor $2, $4, $5
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;
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; MIPS64R2-LABEL: xor_i32:
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; MIPS64R2: # %bb.0: # %entry
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; MIPS64R2-NEXT: xor $1, $4, $5
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; MIPS64R2-NEXT: jr $ra
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; MIPS64R2-NEXT: sll $2, $1, 0
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; MIPS64R2-NEXT: xor $2, $4, $5
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;
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; MIPS64R6-LABEL: xor_i32:
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; MIPS64R6: # %bb.0: # %entry
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; MIPS64R6-NEXT: xor $1, $4, $5
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; MIPS64R6-NEXT: jr $ra
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; MIPS64R6-NEXT: sll $2, $1, 0
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; MIPS64R6-NEXT: xor $2, $4, $5
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;
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; MM32R3-LABEL: xor_i32:
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; MM32R3: # %bb.0: # %entry
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@@ -511,18 +508,21 @@ define signext i32 @xor_i32_4(i32 signext %b) {
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;
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; MIPS64-LABEL: xor_i32_4:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: xori $1, $4, 4
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: xori $2, $4, 4
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; MIPS64-NEXT: sll $2, $1, 0
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;
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; MIPS64R2-LABEL: xor_i32_4:
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; MIPS64R2: # %bb.0: # %entry
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; MIPS64R2-NEXT: xori $1, $4, 4
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; MIPS64R2-NEXT: jr $ra
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; MIPS64R2-NEXT: xori $2, $4, 4
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; MIPS64R2-NEXT: sll $2, $1, 0
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;
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; MIPS64R6-LABEL: xor_i32_4:
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; MIPS64R6: # %bb.0: # %entry
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; MIPS64R6-NEXT: xori $1, $4, 4
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; MIPS64R6-NEXT: jr $ra
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; MIPS64R6-NEXT: xori $2, $4, 4
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; MIPS64R6-NEXT: sll $2, $1, 0
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;
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; MM32R3-LABEL: xor_i32_4:
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; MM32R3: # %bb.0: # %entry
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@@ -118,9 +118,8 @@ define i32 @foo(i32 signext %a) {
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; SHRINK-WRAP-64-STATIC-NEXT: .cfi_def_cfa_offset 16
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; SHRINK-WRAP-64-STATIC-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
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; SHRINK-WRAP-64-STATIC-NEXT: .cfi_offset 31, -8
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; SHRINK-WRAP-64-STATIC-NEXT: addiu $1, $4, 1
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; SHRINK-WRAP-64-STATIC-NEXT: jal f
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; SHRINK-WRAP-64-STATIC-NEXT: sll $4, $1, 0
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; SHRINK-WRAP-64-STATIC-NEXT: addiu $4, $4, 1
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; SHRINK-WRAP-64-STATIC-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
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; SHRINK-WRAP-64-STATIC-NEXT: daddiu $sp, $sp, 16
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; SHRINK-WRAP-64-STATIC-NEXT: .LBB0_2: # %return
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@@ -136,9 +135,8 @@ define i32 @foo(i32 signext %a) {
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; NO-SHRINK-WRAP-64-STATIC-NEXT: beqz $4, .LBB0_2
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; NO-SHRINK-WRAP-64-STATIC-NEXT: nop
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; NO-SHRINK-WRAP-64-STATIC-NEXT: # %bb.1: # %if.end
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; NO-SHRINK-WRAP-64-STATIC-NEXT: addiu $1, $4, 1
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; NO-SHRINK-WRAP-64-STATIC-NEXT: jal f
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; NO-SHRINK-WRAP-64-STATIC-NEXT: sll $4, $1, 0
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; NO-SHRINK-WRAP-64-STATIC-NEXT: addiu $4, $4, 1
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; NO-SHRINK-WRAP-64-STATIC-NEXT: .LBB0_2: # %return
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; NO-SHRINK-WRAP-64-STATIC-NEXT: addiu $2, $zero, 0
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; NO-SHRINK-WRAP-64-STATIC-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
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@@ -158,10 +156,9 @@ define i32 @foo(i32 signext %a) {
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; SHRINK-WRAP-64-PIC-NEXT: .cfi_offset 31, -8
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; SHRINK-WRAP-64-PIC-NEXT: .cfi_offset 28, -16
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; SHRINK-WRAP-64-PIC-NEXT: daddiu $gp, $2, %lo(%neg(%gp_rel(foo)))
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; SHRINK-WRAP-64-PIC-NEXT: addiu $1, $4, 1
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; SHRINK-WRAP-64-PIC-NEXT: ld $25, %call16(f)($gp)
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; SHRINK-WRAP-64-PIC-NEXT: jalr $25
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; SHRINK-WRAP-64-PIC-NEXT: sll $4, $1, 0
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; SHRINK-WRAP-64-PIC-NEXT: addiu $4, $4, 1
|
||||
; SHRINK-WRAP-64-PIC-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
|
||||
; SHRINK-WRAP-64-PIC-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
|
||||
; SHRINK-WRAP-64-PIC-NEXT: daddiu $sp, $sp, 16
|
||||
@@ -182,10 +179,9 @@ define i32 @foo(i32 signext %a) {
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: daddu $2, $1, $25
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: # %bb.1: # %if.end
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: daddiu $gp, $2, %lo(%neg(%gp_rel(foo)))
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: addiu $1, $4, 1
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: ld $25, %call16(f)($gp)
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: jalr $25
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: sll $4, $1, 0
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: addiu $4, $4, 1
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: .LBB0_2: # %return
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: addiu $2, $zero, 0
|
||||
; NO-SHRINK-WRAP-64-PIC-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
|
||||
|
||||
Reference in New Issue
Block a user