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[X86] Override BuildSDIVPow2 for X86.
As noted in PR43197, we can use test+add+cmov+sra to implement signed division by a power of 2. This is based off the similar version in AArch64, but I've adjusted it to use target independent nodes where AArch64 uses target specific CMP and CSEL nodes. I've also blocked INT_MIN as the transform isn't valid for that. I've limited this to i32 and i64 on 64-bit targets for now and only when CMOV is supported. i8 and i16 need further investigation to be sure they get promoted to i32 well. I adjusted a few tests to enable cmov to demonstrate the new codegen. I also changed twoaddr-coalesce-3.ll to 32-bit mode without cmov to avoid perturbing the scenario that is being set up there. Differential Revision: https://reviews.llvm.org/D67087 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371104 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
@@ -20080,6 +20080,61 @@ unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
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return 2;
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}
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SDValue
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X86TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
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SelectionDAG &DAG,
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SmallVectorImpl<SDNode *> &Created) const {
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AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
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if (isIntDivCheap(N->getValueType(0), Attr))
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return SDValue(N,0); // Lower SDIV as SDIV
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assert((Divisor.isPowerOf2() || (-Divisor).isPowerOf2()) &&
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"Unexpected divisor!");
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// Only perform this transform if CMOV is supported otherwise the select
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// below will become a branch.
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if (!Subtarget.hasCMov())
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return SDValue();
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// fold (sdiv X, pow2)
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EVT VT = N->getValueType(0);
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// FIXME: Support i8/i16.
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if ((VT != MVT::i32 && !(Subtarget.is64Bit() && VT == MVT::i64)))
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return SDValue();
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unsigned Lg2 = Divisor.countTrailingZeros();
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// If the divisor is 2 or -2, the default expansion is better.
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if (Lg2 == 1)
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return SDValue();
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SDLoc DL(N);
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SDValue N0 = N->getOperand(0);
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SDValue Zero = DAG.getConstant(0, DL, VT);
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SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
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// If N0 is negative, we need to add (Pow2 - 1) to it before shifting right.
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SDValue Cmp = DAG.getSetCC(DL, MVT::i8, N0, Zero, ISD::SETLT);
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SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
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SDValue CMov = DAG.getNode(ISD::SELECT, DL, VT, Cmp, Add, N0);
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Created.push_back(Cmp.getNode());
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Created.push_back(Add.getNode());
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Created.push_back(CMov.getNode());
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// Divide by pow2.
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SDValue SRA =
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DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i64));
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// If we're dividing by a positive value, we're done. Otherwise, we must
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// negate the result.
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if (Divisor.isNonNegative())
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return SRA;
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Created.push_back(SRA.getNode());
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return DAG.getNode(ISD::SUB, DL, VT, Zero, SRA);
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}
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/// Result of 'and' is compared against zero. Change to a BT node if possible.
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/// Returns the BT node and the condition code needed to use it.
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static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC,
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@@ -1478,6 +1478,9 @@ namespace llvm {
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/// Reassociate floating point divisions into multiply by reciprocal.
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unsigned combineRepeatedFPDivisors() const override;
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SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
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SmallVectorImpl<SDNode *> &Created) const override;
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};
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namespace X86 {
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@@ -3200,10 +3200,9 @@ define i32 @combine_i32_sdiv_pow2(i32 %x) {
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; CHECK-LABEL: combine_i32_sdiv_pow2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarl $31, %eax
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; CHECK-NEXT: shrl $28, %eax
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; CHECK-NEXT: addl %edi, %eax
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; CHECK-NEXT: leal 15(%rdi), %eax
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: cmovnsl %edi, %eax
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; CHECK-NEXT: sarl $4, %eax
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; CHECK-NEXT: retq
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%1 = sdiv i32 %x, 16
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@@ -3214,10 +3213,9 @@ define i32 @combine_i32_sdiv_negpow2(i32 %x) {
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; CHECK-LABEL: combine_i32_sdiv_negpow2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarl $31, %eax
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; CHECK-NEXT: shrl $24, %eax
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; CHECK-NEXT: addl %edi, %eax
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; CHECK-NEXT: leal 255(%rdi), %eax
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: cmovnsl %edi, %eax
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; CHECK-NEXT: sarl $8, %eax
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; CHECK-NEXT: negl %eax
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; CHECK-NEXT: retq
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@@ -3228,10 +3226,9 @@ define i32 @combine_i32_sdiv_negpow2(i32 %x) {
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define i64 @combine_i64_sdiv_pow2(i64 %x) {
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; CHECK-LABEL: combine_i64_sdiv_pow2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: sarq $63, %rax
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; CHECK-NEXT: shrq $60, %rax
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; CHECK-NEXT: addq %rdi, %rax
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; CHECK-NEXT: leaq 15(%rdi), %rax
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: cmovnsq %rdi, %rax
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; CHECK-NEXT: sarq $4, %rax
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; CHECK-NEXT: retq
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%1 = sdiv i64 %x, 16
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@@ -3241,10 +3238,9 @@ define i64 @combine_i64_sdiv_pow2(i64 %x) {
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define i64 @combine_i64_sdiv_negpow2(i64 %x) {
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; CHECK-LABEL: combine_i64_sdiv_negpow2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: sarq $63, %rax
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; CHECK-NEXT: shrq $56, %rax
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; CHECK-NEXT: addq %rdi, %rax
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; CHECK-NEXT: leaq 255(%rdi), %rax
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: cmovnsq %rdi, %rax
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; CHECK-NEXT: sarq $8, %rax
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; CHECK-NEXT: negq %rax
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; CHECK-NEXT: retq
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@@ -56,10 +56,9 @@ define i32 @combine_srem_by_minsigned(i32 %x) {
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; CHECK-LABEL: combine_srem_by_minsigned:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarl $31, %eax
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; CHECK-NEXT: shrl %eax
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; CHECK-NEXT: addl %edi, %eax
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; CHECK-NEXT: leal 2147483647(%rdi), %eax
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: cmovnsl %edi, %eax
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; CHECK-NEXT: andl $-2147483648, %eax # imm = 0x80000000
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; CHECK-NEXT: addl %edi, %eax
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; CHECK-NEXT: retq
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@@ -513,12 +512,12 @@ define i32 @combine_srem_pow2(i32 %x) {
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; CHECK-LABEL: combine_srem_pow2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: movl %edi, %ecx
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; CHECK-NEXT: sarl $31, %ecx
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; CHECK-NEXT: shrl $28, %ecx
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; CHECK-NEXT: addl %edi, %ecx
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; CHECK-NEXT: leal 15(%rax), %ecx
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: cmovnsl %edi, %ecx
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; CHECK-NEXT: andl $-16, %ecx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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%1 = srem i32 %x, 16
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ret i32 %1
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@@ -528,12 +527,12 @@ define i32 @combine_srem_negpow2(i32 %x) {
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; CHECK-LABEL: combine_srem_negpow2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: movl %edi, %ecx
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; CHECK-NEXT: sarl $31, %ecx
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; CHECK-NEXT: shrl $24, %ecx
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; CHECK-NEXT: addl %edi, %ecx
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; CHECK-NEXT: leal 255(%rax), %ecx
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: cmovnsl %edi, %ecx
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; CHECK-NEXT: andl $-256, %ecx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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%1 = srem i32 %x, -256
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ret i32 %1
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@@ -543,10 +542,9 @@ define i64 @combine_i64_srem_pow2(i64 %x) {
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; CHECK-LABEL: combine_i64_srem_pow2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: movq %rdi, %rcx
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; CHECK-NEXT: sarq $63, %rcx
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; CHECK-NEXT: shrq $60, %rcx
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; CHECK-NEXT: addq %rdi, %rcx
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; CHECK-NEXT: leaq 15(%rdi), %rcx
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: cmovnsq %rdi, %rcx
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; CHECK-NEXT: andq $-16, %rcx
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; CHECK-NEXT: subq %rcx, %rax
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; CHECK-NEXT: retq
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@@ -558,10 +556,9 @@ define i64 @combine_i64_srem_negpow2(i64 %x) {
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; CHECK-LABEL: combine_i64_srem_negpow2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: movq %rdi, %rcx
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; CHECK-NEXT: sarq $63, %rcx
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; CHECK-NEXT: shrq $56, %rcx
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; CHECK-NEXT: addq %rdi, %rcx
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; CHECK-NEXT: leaq 255(%rdi), %rcx
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: cmovnsq %rdi, %rcx
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; CHECK-NEXT: andq $-256, %rcx
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; CHECK-NEXT: subq %rcx, %rax
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; CHECK-NEXT: retq
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@@ -27,10 +27,9 @@ define i32 @test2(i32 %X) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: sarl $31, %ecx
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; CHECK-NEXT: shrl $24, %ecx
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; CHECK-NEXT: addl %eax, %ecx
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; CHECK-NEXT: leal 255(%eax), %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: cmovnsl %eax, %ecx
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; CHECK-NEXT: andl $-256, %ecx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: retl
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@@ -318,10 +318,9 @@ define i32 @test_srem_pow2(i32 %X) nounwind {
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; X86-LABEL: test_srem_pow2:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %edx
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; X86-NEXT: sarl $31, %edx
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; X86-NEXT: shrl $28, %edx
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; X86-NEXT: addl %ecx, %edx
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; X86-NEXT: leal 15(%ecx), %edx
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; X86-NEXT: testl %ecx, %ecx
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; X86-NEXT: cmovnsl %ecx, %edx
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; X86-NEXT: andl $-16, %edx
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: cmpl %edx, %ecx
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@@ -330,10 +329,10 @@ define i32 @test_srem_pow2(i32 %X) nounwind {
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;
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; X64-LABEL: test_srem_pow2:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: sarl $31, %ecx
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; X64-NEXT: shrl $28, %ecx
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; X64-NEXT: addl %edi, %ecx
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: leal 15(%rdi), %ecx
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; X64-NEXT: testl %edi, %edi
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; X64-NEXT: cmovnsl %edi, %ecx
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; X64-NEXT: andl $-16, %ecx
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: cmpl %ecx, %edi
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@@ -350,10 +349,9 @@ define i32 @test_srem_int_min(i32 %X) nounwind {
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; X86-LABEL: test_srem_int_min:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %edx
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; X86-NEXT: sarl $31, %edx
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; X86-NEXT: shrl %edx
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; X86-NEXT: addl %ecx, %edx
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; X86-NEXT: leal 2147483647(%ecx), %edx
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; X86-NEXT: testl %ecx, %ecx
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; X86-NEXT: cmovnsl %ecx, %edx
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; X86-NEXT: andl $-2147483648, %edx # imm = 0x80000000
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: addl %ecx, %edx
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@@ -362,10 +360,10 @@ define i32 @test_srem_int_min(i32 %X) nounwind {
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;
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; X64-LABEL: test_srem_int_min:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: sarl $31, %ecx
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; X64-NEXT: shrl %ecx
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; X64-NEXT: addl %edi, %ecx
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: leal 2147483647(%rdi), %ecx
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; X64-NEXT: testl %edi, %edi
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; X64-NEXT: cmovnsl %edi, %ecx
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; X64-NEXT: andl $-2147483648, %ecx # imm = 0x80000000
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: addl %edi, %ecx
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