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[mips] Correct microMIP's jump and add unconditional branch pseudo

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Correct the definition of 'j' as being unavailable for microMIPS32R6 and
provide the 'b' assembly idiom for codegen purposes for microMIPS32r3.

Provide the necessary 'br' pattern for microMIPS32R6 as it now longer
incorrectly uses the 'j' instruction.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D39741


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317801 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis 2017-11-09 16:02:18 +00:00
parent 2fe0076f87
commit 5be95c6164
6 changed files with 63 additions and 27 deletions
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4
lib/Target/Mips/MicroMips32r6InstrInfo.td
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@ -383,7 +383,9 @@ class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
bit isCall = 1;
list<Register> Defs = [RA];
}
class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC>;
class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> {
list<dag> Pattern = [(br bb:$offset)];
}
class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
!strconcat("bc16", "\t$offset"), [],

12
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -889,9 +889,14 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
EXT_FM_MM<0x0c>;
/// Jump Instructions
}
let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeJumpTargetMM" in
def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
let DecoderMethod = "DecodeJumpTargetMM" in {
def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
J_FM_MM<0x35>;
def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
}
@ -926,6 +931,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
GPR32Opnd>, BGEZAL_FM_MM<0x13>;
def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
GPR32Opnd>, BGEZAL_FM_MM<0x11>;
}
def B_MM : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch, ISA_MICROMIPS;
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
/// Control Instructions
def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;

9
lib/Target/Mips/MipsInstrInfo.td
View File

@ -1488,9 +1488,9 @@ class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
}
// Unconditional branch
class UncondBranch<Instruction BEQInst> :
class UncondBranch<Instruction BEQInst, DAGOperand opnd> :
PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
PseudoInstExpansion<(BEQInst ZERO, ZERO, opnd:$offset)> {
let isBranch = 1;
let isTerminator = 1;
let isBarrier = 1;
@ -2045,7 +2045,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6;
/// Jump and Branch Instructions
def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
AdditionalRequires<[RelocNotPIC]>, IsBranch;
AdditionalRequires<[RelocNotPIC, NotInMicroMips]>, IsBranch;
def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
@ -2069,7 +2069,8 @@ def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
BGEZ_FM<1, 0>;
def BLTZL : MMRel, CBranchZeroLikely<"bltzl", brtarget, GPR32Opnd>,
BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
def B : UncondBranch<BEQ>;
def B : UncondBranch<BEQ, brtarget>,
AdditionalRequires<[NotInMicroMips]>;
def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
let AdditionalPredicates = [NotInMicroMips] in {

22
lib/Target/Mips/MipsSEInstrInfo.cpp
View File

@ -540,17 +540,17 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC ||
Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC ||
Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC ||
Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC ||
Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BEQZC64 ||
Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
Opc == Mips::BLEZC64 || Opc == Mips::BC || Opc == Mips::BBIT0 ||
Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
Opc == Mips::B_MM || Opc == Mips::BEQZC_MM ||
Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC ||
Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC ||
Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC ||
Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC ||
Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
Opc == Mips::BBIT132) ? Opc : 0;
}

26
test/CodeGen/Mips/br-jmp.ll
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@ -1,7 +1,13 @@
; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC
; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC16
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16
; RUN: llc -asm-show-inst -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC
; RUN: llc -asm-show-inst -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC
; RUN: llc -asm-show-inst -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC16
; RUN: llc -asm-show-inst -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC16
; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMM
; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PICMM
; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMMR6
; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC
define void @count(i32 %x, i32 %y, i32 %z) noreturn nounwind readnone {
entry:
@ -11,8 +17,10 @@ bosco: ; preds = %bosco, %entry
br label %bosco
}
; CHECK-PIC: b $BB0_1
; CHECK-STATIC: j $BB0_1
; CHECK-PIC16: b $BB0_1
; CHECK-STATIC16: b $BB0_1
; PIC: b $BB0_1 # <MCInst #{{.*}} BEQ
; PICMM: b $BB0_1 # <MCInst #{{.*}} BEQ_MM
; STATIC: j $BB0_1 # <MCInst #{{.*}} J
; STATICMM: j $BB0_1 # <MCInst #{{.*}} J_MM
; STATICMMR6: bc $BB0_1 # <MCInst #{{.*}} BC_MMR6
; PIC16: b $BB0_1
; STATIC16: b $BB0_1

17
test/MC/Mips/j-macro-insn.s Normal file
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@ -0,0 +1,17 @@
# RUN: llvm-mc -arch=mips -show-inst %s | FileCheck --check-prefix=STATIC %s
# RUN: llvm-mc -arch=mips -position-independent -show-inst %s | FileCheck --check-prefix=PIC %s
# RUN: llvm-mc -arch=mips -mattr=+micromips -show-inst %s | FileCheck --check-prefix=STATIC-MM %s
# RUN: llvm-mc -arch=mips -mattr=+micromips -position-independent -show-inst %s | FileCheck --check-prefix=PIC-MM %s
.text
j foo
nop
foo:
nop
b foo
# PIC: b foo # <MCInst #{{[0-9]+}} BEQ
# STATIC: j foo # <MCInst #{{[0-9]+}} J
# PIC-MM: b foo # <MCInst #{{[0-9]+}} BEQ_MM
# STATIC-MM: j foo # <MCInst #{{[0-9]+}} J_MM