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[ARM] Split large widening MVE loads
Similar to rL372717, we can force the splitting of extends of vector loads in MVE, in order to use the better widening loads as opposed to going through expensive extends. This adds a combine to early-on detect extends of loads and split the load in two, from where normal legalisation will kick in and we get a series of widening loads. Differential Revision: https://reviews.llvm.org/D67909 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Green
@@ -898,9 +898,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::SHL);
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::SIGN_EXTEND);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::ANY_EXTEND);
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setTargetDAGCombine(ISD::FP_TO_SINT);
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setTargetDAGCombine(ISD::FP_TO_UINT);
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setTargetDAGCombine(ISD::FDIV);
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@@ -922,6 +919,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
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setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::SIGN_EXTEND);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::ANY_EXTEND);
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}
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if (!Subtarget->hasFP64()) {
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@@ -13694,6 +13694,71 @@ static SDValue PerformShiftCombine(SDNode *N,
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return SDValue();
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}
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// Look for a sign/zero extend of a larger than legal load. This can be split
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// into two extending loads, which are simpler to deal with than an arbitrary
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// sign extend.
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SDValue PerformSplittingToWideningLoad(SDNode *N, SelectionDAG &DAG) {
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SDValue N0 = N->getOperand(0);
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if (N0.getOpcode() != ISD::LOAD)
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return SDValue();
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LoadSDNode *LD = cast<LoadSDNode>(N0.getNode());
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if (!LD->isSimple() || !N0.hasOneUse() || LD->isIndexed() ||
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LD->getExtensionType() != ISD::NON_EXTLOAD)
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return SDValue();
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EVT FromVT = LD->getValueType(0);
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EVT ToVT = N->getValueType(0);
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if (!ToVT.isVector())
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return SDValue();
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assert(FromVT.getVectorNumElements() == ToVT.getVectorNumElements());
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EVT ToEltVT = ToVT.getVectorElementType();
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EVT FromEltVT = FromVT.getVectorElementType();
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unsigned NumElements = 0;
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if (ToEltVT == MVT::i32 && (FromEltVT == MVT::i16 || FromEltVT == MVT::i8))
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NumElements = 4;
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if (ToEltVT == MVT::i16 && FromEltVT == MVT::i8)
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NumElements = 8;
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if (NumElements == 0 ||
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FromVT.getVectorNumElements() == NumElements ||
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FromVT.getVectorNumElements() % NumElements != 0 ||
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!isPowerOf2_32(NumElements))
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return SDValue();
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SDLoc DL(LD);
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// Details about the old load
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SDValue Ch = LD->getChain();
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SDValue BasePtr = LD->getBasePtr();
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unsigned Alignment = LD->getOriginalAlignment();
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MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
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AAMDNodes AAInfo = LD->getAAInfo();
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ISD::LoadExtType NewExtType =
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N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
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SDValue Offset = DAG.getUNDEF(BasePtr.getValueType());
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EVT NewFromVT = FromVT.getHalfNumVectorElementsVT(*DAG.getContext());
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EVT NewToVT = ToVT.getHalfNumVectorElementsVT(*DAG.getContext());
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unsigned NewOffset = NewFromVT.getSizeInBits() / 8;
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SDValue NewPtr = DAG.getObjectPtrOffset(DL, BasePtr, NewOffset);
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// Split the load in half, each side of which is extended separately. This
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// is good enough, as legalisation will take it from there. They are either
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// already legal or they will be split further into something that is
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// legal.
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SDValue NewLoad1 =
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DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, BasePtr, Offset,
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LD->getPointerInfo(), NewFromVT, Alignment, MMOFlags, AAInfo);
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SDValue NewLoad2 =
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DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset,
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LD->getPointerInfo().getWithOffset(NewOffset), NewFromVT,
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Alignment, MMOFlags, AAInfo);
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SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
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SDValue(NewLoad1.getNode(), 1),
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SDValue(NewLoad2.getNode(), 1));
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DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewChain);
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, NewLoad1, NewLoad2);
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}
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/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
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/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
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static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
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@@ -13731,6 +13796,10 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
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}
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}
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if (ST->hasMVEIntegerOps())
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if (SDValue NewLoad = PerformSplittingToWideningLoad(N, DAG))
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return NewLoad;
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return SDValue();
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}
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@@ -134,51 +134,14 @@ entry:
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define void @foo_int32_int8_double(<16 x i32>* %dest, <16 x i8>* readonly %src, i32 %n) {
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; CHECK-LABEL: foo_int32_int8_double:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.u8 q0, [r1]
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; CHECK-NEXT: vmov.u8 r1, q0[12]
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; CHECK-NEXT: vmov.32 q1[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[13]
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; CHECK-NEXT: vmov.32 q1[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[14]
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; CHECK-NEXT: vmov.32 q1[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[15]
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; CHECK-NEXT: vmov.32 q1[3], r1
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; CHECK-NEXT: vmov.u8 r1, q0[8]
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; CHECK-NEXT: vmovlb.s8 q1, q1
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; CHECK-NEXT: vmovlb.s16 q1, q1
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; CHECK-NEXT: vstrw.32 q1, [r0, #48]
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; CHECK-NEXT: vmov.32 q1[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[9]
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; CHECK-NEXT: vmov.32 q1[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[10]
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; CHECK-NEXT: vmov.32 q1[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[11]
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; CHECK-NEXT: vmov.32 q1[3], r1
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; CHECK-NEXT: vmov.u8 r1, q0[4]
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; CHECK-NEXT: vmovlb.s8 q1, q1
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; CHECK-NEXT: vmovlb.s16 q1, q1
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; CHECK-NEXT: vstrw.32 q1, [r0, #32]
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; CHECK-NEXT: vmov.32 q1[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[5]
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; CHECK-NEXT: vmov.32 q1[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[6]
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; CHECK-NEXT: vmov.32 q1[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[7]
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; CHECK-NEXT: vmov.32 q1[3], r1
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; CHECK-NEXT: vmov.u8 r1, q0[0]
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; CHECK-NEXT: vmovlb.s8 q1, q1
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; CHECK-NEXT: vmovlb.s16 q1, q1
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; CHECK-NEXT: vstrw.32 q1, [r0, #16]
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; CHECK-NEXT: vmov.32 q1[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[1]
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; CHECK-NEXT: vmov.32 q1[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[2]
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; CHECK-NEXT: vmov.32 q1[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[3]
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; CHECK-NEXT: vmov.32 q1[3], r1
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; CHECK-NEXT: vmovlb.s8 q0, q1
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: vldrb.s32 q0, [r1, #4]
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; CHECK-NEXT: vldrb.s32 q1, [r1]
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; CHECK-NEXT: vldrb.s32 q2, [r1, #12]
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; CHECK-NEXT: vldrb.s32 q3, [r1, #8]
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; CHECK-NEXT: vstrw.32 q1, [r0]
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; CHECK-NEXT: vstrw.32 q0, [r0, #16]
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; CHECK-NEXT: vstrw.32 q3, [r0, #32]
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; CHECK-NEXT: vstrw.32 q2, [r0, #48]
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; CHECK-NEXT: bx lr
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entry:
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%wide.load = load <16 x i8>, <16 x i8>* %src, align 1
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@@ -190,42 +153,9 @@ entry:
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define void @foo_int16_int8_double(<16 x i16>* %dest, <16 x i8>* readonly %src, i32 %n) {
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; CHECK-LABEL: foo_int16_int8_double:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.u8 q0, [r1]
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; CHECK-NEXT: vmov.u8 r1, q0[8]
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; CHECK-NEXT: vmov.16 q1[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[9]
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; CHECK-NEXT: vmov.16 q1[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[10]
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; CHECK-NEXT: vmov.16 q1[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[11]
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; CHECK-NEXT: vmov.16 q1[3], r1
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; CHECK-NEXT: vmov.u8 r1, q0[12]
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; CHECK-NEXT: vmov.16 q1[4], r1
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; CHECK-NEXT: vmov.u8 r1, q0[13]
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; CHECK-NEXT: vmov.16 q1[5], r1
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; CHECK-NEXT: vmov.u8 r1, q0[14]
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; CHECK-NEXT: vmov.16 q1[6], r1
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; CHECK-NEXT: vmov.u8 r1, q0[15]
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; CHECK-NEXT: vmov.16 q1[7], r1
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; CHECK-NEXT: vmov.u8 r1, q0[0]
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; CHECK-NEXT: vmovlb.s8 q1, q1
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; CHECK-NEXT: vldrb.s16 q0, [r1]
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; CHECK-NEXT: vldrb.s16 q1, [r1, #8]
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; CHECK-NEXT: vstrh.16 q1, [r0, #16]
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; CHECK-NEXT: vmov.16 q1[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[1]
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; CHECK-NEXT: vmov.16 q1[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[2]
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; CHECK-NEXT: vmov.16 q1[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[3]
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; CHECK-NEXT: vmov.16 q1[3], r1
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; CHECK-NEXT: vmov.u8 r1, q0[4]
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; CHECK-NEXT: vmov.16 q1[4], r1
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; CHECK-NEXT: vmov.u8 r1, q0[5]
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; CHECK-NEXT: vmov.16 q1[5], r1
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; CHECK-NEXT: vmov.u8 r1, q0[6]
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; CHECK-NEXT: vmov.16 q1[6], r1
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; CHECK-NEXT: vmov.u8 r1, q0[7]
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; CHECK-NEXT: vmov.16 q1[7], r1
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; CHECK-NEXT: vmovlb.s8 q0, q1
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; CHECK-NEXT: vstrh.16 q0, [r0]
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; CHECK-NEXT: bx lr
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entry:
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@@ -238,26 +168,9 @@ entry:
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define void @foo_int32_int16_double(<8 x i32>* %dest, <8 x i16>* readonly %src, i32 %n) {
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; CHECK-LABEL: foo_int32_int16_double:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.u16 q0, [r1]
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; CHECK-NEXT: vmov.u16 r1, q0[4]
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; CHECK-NEXT: vmov.32 q1[0], r1
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; CHECK-NEXT: vmov.u16 r1, q0[5]
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; CHECK-NEXT: vmov.32 q1[1], r1
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; CHECK-NEXT: vmov.u16 r1, q0[6]
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; CHECK-NEXT: vmov.32 q1[2], r1
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; CHECK-NEXT: vmov.u16 r1, q0[7]
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; CHECK-NEXT: vmov.32 q1[3], r1
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; CHECK-NEXT: vmov.u16 r1, q0[0]
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; CHECK-NEXT: vmovlb.s16 q1, q1
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; CHECK-NEXT: vldrh.s32 q0, [r1]
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; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
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; CHECK-NEXT: vstrw.32 q1, [r0, #16]
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; CHECK-NEXT: vmov.32 q1[0], r1
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; CHECK-NEXT: vmov.u16 r1, q0[1]
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; CHECK-NEXT: vmov.32 q1[1], r1
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; CHECK-NEXT: vmov.u16 r1, q0[2]
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; CHECK-NEXT: vmov.32 q1[2], r1
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; CHECK-NEXT: vmov.u16 r1, q0[3]
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; CHECK-NEXT: vmov.32 q1[3], r1
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; CHECK-NEXT: vmovlb.s16 q0, q1
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: bx lr
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entry:
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@@ -311,48 +224,14 @@ entry:
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define void @foo_uint32_uint8_double(<16 x i32>* %dest, <16 x i8>* readonly %src, i32 %n) {
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; CHECK-LABEL: foo_uint32_uint8_double:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.u8 q0, [r1]
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; CHECK-NEXT: vmov.i32 q1, #0xff
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; CHECK-NEXT: vmov.u8 r1, q0[12]
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; CHECK-NEXT: vmov.32 q2[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[13]
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; CHECK-NEXT: vmov.32 q2[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[14]
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; CHECK-NEXT: vmov.32 q2[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[15]
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; CHECK-NEXT: vmov.32 q2[3], r1
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; CHECK-NEXT: vmov.u8 r1, q0[8]
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; CHECK-NEXT: vand q2, q2, q1
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; CHECK-NEXT: vldrb.u32 q0, [r1, #4]
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; CHECK-NEXT: vldrb.u32 q1, [r1]
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; CHECK-NEXT: vldrb.u32 q2, [r1, #12]
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; CHECK-NEXT: vldrb.u32 q3, [r1, #8]
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; CHECK-NEXT: vstrw.32 q1, [r0]
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; CHECK-NEXT: vstrw.32 q0, [r0, #16]
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; CHECK-NEXT: vstrw.32 q3, [r0, #32]
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; CHECK-NEXT: vstrw.32 q2, [r0, #48]
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; CHECK-NEXT: vmov.32 q2[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[9]
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; CHECK-NEXT: vmov.32 q2[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[10]
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; CHECK-NEXT: vmov.32 q2[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[11]
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; CHECK-NEXT: vmov.32 q2[3], r1
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; CHECK-NEXT: vmov.u8 r1, q0[4]
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; CHECK-NEXT: vand q2, q2, q1
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; CHECK-NEXT: vstrw.32 q2, [r0, #32]
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; CHECK-NEXT: vmov.32 q2[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[5]
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; CHECK-NEXT: vmov.32 q2[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[6]
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; CHECK-NEXT: vmov.32 q2[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[7]
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; CHECK-NEXT: vmov.32 q2[3], r1
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; CHECK-NEXT: vmov.u8 r1, q0[0]
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; CHECK-NEXT: vand q2, q2, q1
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; CHECK-NEXT: vstrw.32 q2, [r0, #16]
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; CHECK-NEXT: vmov.32 q2[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[1]
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; CHECK-NEXT: vmov.32 q2[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[2]
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; CHECK-NEXT: vmov.32 q2[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[3]
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; CHECK-NEXT: vmov.32 q2[3], r1
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; CHECK-NEXT: vand q0, q2, q1
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%wide.load = load <16 x i8>, <16 x i8>* %src, align 1
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@@ -364,42 +243,9 @@ entry:
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define void @foo_uint16_uint8_double(<16 x i16>* %dest, <16 x i8>* readonly %src, i32 %n) {
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; CHECK-LABEL: foo_uint16_uint8_double:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.u8 q0, [r1]
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; CHECK-NEXT: vmov.u8 r1, q0[8]
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; CHECK-NEXT: vmov.16 q1[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[9]
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; CHECK-NEXT: vmov.16 q1[1], r1
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; CHECK-NEXT: vmov.u8 r1, q0[10]
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; CHECK-NEXT: vmov.16 q1[2], r1
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; CHECK-NEXT: vmov.u8 r1, q0[11]
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; CHECK-NEXT: vmov.16 q1[3], r1
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; CHECK-NEXT: vmov.u8 r1, q0[12]
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; CHECK-NEXT: vmov.16 q1[4], r1
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; CHECK-NEXT: vmov.u8 r1, q0[13]
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; CHECK-NEXT: vmov.16 q1[5], r1
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; CHECK-NEXT: vmov.u8 r1, q0[14]
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; CHECK-NEXT: vmov.16 q1[6], r1
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; CHECK-NEXT: vmov.u8 r1, q0[15]
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; CHECK-NEXT: vmov.16 q1[7], r1
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; CHECK-NEXT: vmov.u8 r1, q0[0]
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; CHECK-NEXT: vmovlb.u8 q1, q1
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; CHECK-NEXT: vldrb.u16 q0, [r1]
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; CHECK-NEXT: vldrb.u16 q1, [r1, #8]
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; CHECK-NEXT: vstrh.16 q1, [r0, #16]
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; CHECK-NEXT: vmov.16 q1[0], r1
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; CHECK-NEXT: vmov.u8 r1, q0[1]
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; CHECK-NEXT: vmov.16 q1[1], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[2]
|
||||
; CHECK-NEXT: vmov.16 q1[2], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[3]
|
||||
; CHECK-NEXT: vmov.16 q1[3], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[4]
|
||||
; CHECK-NEXT: vmov.16 q1[4], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[5]
|
||||
; CHECK-NEXT: vmov.16 q1[5], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[6]
|
||||
; CHECK-NEXT: vmov.16 q1[6], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[7]
|
||||
; CHECK-NEXT: vmov.16 q1[7], r1
|
||||
; CHECK-NEXT: vmovlb.u8 q0, q1
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@@ -412,26 +258,9 @@ entry:
|
||||
define void @foo_uint32_uint16_double(<8 x i32>* %dest, <8 x i16>* readonly %src, i32 %n) {
|
||||
; CHECK-LABEL: foo_uint32_uint16_double:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[4]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[5]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[6]
|
||||
; CHECK-NEXT: vmov.32 q1[2], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[7]
|
||||
; CHECK-NEXT: vmov.32 q1[3], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[0]
|
||||
; CHECK-NEXT: vmovlb.u16 q1, q1
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vldrh.u32 q1, [r1, #8]
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[1]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[2]
|
||||
; CHECK-NEXT: vmov.32 q1[2], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[3]
|
||||
; CHECK-NEXT: vmov.32 q1[3], r1
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q1
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@@ -445,34 +274,18 @@ entry:
|
||||
define void @foo_int32_int8_both(<16 x i32>* %dest, <16 x i8>* readonly %src, i32 %n) {
|
||||
; CHECK-LABEL: foo_int32_int8_both:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1]
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[8]
|
||||
; CHECK-NEXT: vmov.16 q1[0], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[9]
|
||||
; CHECK-NEXT: vmov.16 q1[1], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[10]
|
||||
; CHECK-NEXT: vmov.16 q1[2], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[11]
|
||||
; CHECK-NEXT: vmov.16 q1[3], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[12]
|
||||
; CHECK-NEXT: vmov.16 q1[4], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[13]
|
||||
; CHECK-NEXT: vmov.16 q1[5], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[14]
|
||||
; CHECK-NEXT: vmov.16 q1[6], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[15]
|
||||
; CHECK-NEXT: vmov.16 q1[7], r1
|
||||
; CHECK-NEXT: vmovlb.s8 q1, q1
|
||||
; CHECK-NEXT: vmov.u16 r1, q1[4]
|
||||
; CHECK-NEXT: vmov.32 q2[0], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q1[5]
|
||||
; CHECK-NEXT: vmov.32 q2[1], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q1[6]
|
||||
; CHECK-NEXT: vmov.32 q2[2], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q1[7]
|
||||
; CHECK-NEXT: vmov.32 q2[3], r1
|
||||
; CHECK-NEXT: vldrb.s16 q1, [r1, #8]
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[4]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[5]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[6]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[7]
|
||||
; CHECK-NEXT: vmov.32 q0[3], r2
|
||||
; CHECK-NEXT: vmovlb.u16 q2, q0
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r1]
|
||||
; CHECK-NEXT: vmov.u16 r1, q1[0]
|
||||
; CHECK-NEXT: vmovlb.u16 q2, q2
|
||||
; CHECK-NEXT: vstrw.32 q2, [r0, #48]
|
||||
; CHECK-NEXT: vmov.32 q2[0], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q1[1]
|
||||
@@ -481,26 +294,9 @@ define void @foo_int32_int8_both(<16 x i32>* %dest, <16 x i8>* readonly %src, i3
|
||||
; CHECK-NEXT: vmov.32 q2[2], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q1[3]
|
||||
; CHECK-NEXT: vmov.32 q2[3], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[0]
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[4]
|
||||
; CHECK-NEXT: vmovlb.u16 q1, q2
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0, #32]
|
||||
; CHECK-NEXT: vmov.16 q1[0], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[1]
|
||||
; CHECK-NEXT: vmov.16 q1[1], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[2]
|
||||
; CHECK-NEXT: vmov.16 q1[2], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[3]
|
||||
; CHECK-NEXT: vmov.16 q1[3], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[4]
|
||||
; CHECK-NEXT: vmov.16 q1[4], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[5]
|
||||
; CHECK-NEXT: vmov.16 q1[5], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[6]
|
||||
; CHECK-NEXT: vmov.16 q1[6], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[7]
|
||||
; CHECK-NEXT: vmov.16 q1[7], r1
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q1
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[4]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q0[5]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r1
|
||||
@@ -532,27 +328,10 @@ entry:
|
||||
define <8 x i16>* @foo_uint32_uint16_double_offset(<8 x i32>* %dest, <8 x i16>* readonly %src, i32 %n) {
|
||||
; CHECK-LABEL: foo_uint32_uint16_double_offset:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1, #16]!
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[4]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[5]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[6]
|
||||
; CHECK-NEXT: vmov.32 q1[2], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[7]
|
||||
; CHECK-NEXT: vmov.32 q1[3], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[0]
|
||||
; CHECK-NEXT: vmovlb.s16 q1, q1
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[1]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[2]
|
||||
; CHECK-NEXT: vmov.32 q1[2], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[3]
|
||||
; CHECK-NEXT: vmov.32 q1[3], r2
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q1
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1, #16]!
|
||||
; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0, #16]
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@@ -566,48 +345,14 @@ entry:
|
||||
define <16 x i16>* @foo_uint32_uint16_quad_offset(<16 x i32>* %dest, <16 x i16>* readonly %src, i32 %n) {
|
||||
; CHECK-LABEL: foo_uint32_uint16_quad_offset:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q1, [r1, #32]!
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[4]
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[5]
|
||||
; CHECK-NEXT: vmov.32 q0[1], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[6]
|
||||
; CHECK-NEXT: vmov.32 q0[2], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[7]
|
||||
; CHECK-NEXT: vmov.32 q0[3], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[0]
|
||||
; CHECK-NEXT: vmovlb.s16 q2, q0
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1, #16]
|
||||
; CHECK-NEXT: vstrw.32 q2, [r0, #16]
|
||||
; CHECK-NEXT: vmov.32 q2[0], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[1]
|
||||
; CHECK-NEXT: vmov.32 q2[1], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[2]
|
||||
; CHECK-NEXT: vmov.32 q2[2], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q1[3]
|
||||
; CHECK-NEXT: vmov.32 q2[3], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[4]
|
||||
; CHECK-NEXT: vmovlb.s16 q1, q2
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[5]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[6]
|
||||
; CHECK-NEXT: vmov.32 q1[2], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[7]
|
||||
; CHECK-NEXT: vmov.32 q1[3], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[0]
|
||||
; CHECK-NEXT: vmovlb.s16 q1, q1
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0, #48]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[1]
|
||||
; CHECK-NEXT: vmov.32 q1[1], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[2]
|
||||
; CHECK-NEXT: vmov.32 q1[2], r2
|
||||
; CHECK-NEXT: vmov.u16 r2, q0[3]
|
||||
; CHECK-NEXT: vmov.32 q1[3], r2
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q1
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0, #32]
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1, #32]!
|
||||
; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
|
||||
; CHECK-NEXT: vldrh.s32 q2, [r1, #24]
|
||||
; CHECK-NEXT: vldrh.s32 q3, [r1, #16]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrw.32 q2, [r0, #48]
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vstrw.32 q3, [r0, #32]
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
|
||||
Reference in New Issue
Block a user