gn build: Add Mips target

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363159 91177308-0d34-0410-b5e6-96231b3b80d8

utils/gn/TODO.txt

@@ -4,7 +4,7 @@ Ideas for things to do:
   - once there are more projects, have an llvm_enable_projects arg, modeled
     after llvm_targets_to_build in the GN build
   - a check-all build target that runs test of all projects
-- more targets (AVR MIPS RISCV SystemZ etc)
+- more targets (AMDGPU ARC AVR MSP430 NVPTX SystemZ XCore)
   - example: https://reviews.llvm.org/D56416
 - investigate feasibility of working `gn check`
 

utils/gn/secondary/llvm/lib/Target/Mips/AsmParser/BUILD.gn

@@ -0,0 +1,23 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("MipsGenAsmMatcher") {
+  visibility = [ ":AsmParser" ]
+  args = [ "-gen-asm-matcher" ]
+  td_file = "../Mips.td"
+}
+
+static_library("AsmParser") {
+  output_name = "LLVMMipsAsmParser"
+  deps = [
+    ":MipsGenAsmMatcher",
+    "//llvm/lib/MC",
+    "//llvm/lib/MC/MCParser",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/Mips/MCTargetDesc",
+    "//llvm/lib/Target/Mips/TargetInfo",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "MipsAsmParser.cpp",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn

@@ -0,0 +1,118 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("MipsGenCallingConv") {
+  visibility = [ ":LLVMMipsCodeGen" ]
+  args = [ "-gen-callingconv" ]
+  td_file = "Mips.td"
+}
+
+tablegen("MipsGenDAGISel") {
+  visibility = [ ":LLVMMipsCodeGen" ]
+  args = [ "-gen-dag-isel" ]
+  td_file = "Mips.td"
+}
+
+tablegen("MipsGenFastISel") {
+  visibility = [ ":LLVMMipsCodeGen" ]
+  args = [ "-gen-fast-isel" ]
+  td_file = "Mips.td"
+}
+
+tablegen("MipsGenGlobalISel") {
+  visibility = [ ":LLVMMipsCodeGen" ]
+  args = [ "-gen-global-isel" ]
+  td_file = "Mips.td"
+}
+
+tablegen("MipsGenMCPseudoLowering") {
+  visibility = [ ":LLVMMipsCodeGen" ]
+  args = [ "-gen-pseudo-lowering" ]
+  td_file = "Mips.td"
+}
+
+tablegen("MipsGenRegisterBank") {
+  visibility = [ ":LLVMMipsCodeGen" ]
+  args = [ "-gen-register-bank" ]
+  td_file = "Mips.td"
+}
+
+static_library("LLVMMipsCodeGen") {
+  deps = [
+    ":MipsGenCallingConv",
+    ":MipsGenDAGISel",
+    ":MipsGenFastISel",
+    ":MipsGenGlobalISel",
+    ":MipsGenMCPseudoLowering",
+    ":MipsGenRegisterBank",
+    "MCTargetDesc",
+    "TargetInfo",
+    "//llvm/include/llvm/Config:llvm-config",
+    "//llvm/lib/Analysis",
+    "//llvm/lib/CodeGen",
+    "//llvm/lib/CodeGen/AsmPrinter",
+    "//llvm/lib/CodeGen/GlobalISel",
+    "//llvm/lib/CodeGen/SelectionDAG",
+    "//llvm/lib/IR",
+    "//llvm/lib/MC",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target",
+  ]
+  include_dirs = [ "." ]
+  sources = [
+    "MicroMipsSizeReduction.cpp",
+    "Mips16FrameLowering.cpp",
+    "Mips16HardFloat.cpp",
+    "Mips16HardFloatInfo.cpp",
+    "Mips16ISelDAGToDAG.cpp",
+    "Mips16ISelLowering.cpp",
+    "Mips16InstrInfo.cpp",
+    "Mips16RegisterInfo.cpp",
+    "MipsAnalyzeImmediate.cpp",
+    "MipsAsmPrinter.cpp",
+    "MipsBranchExpansion.cpp",
+    "MipsCCState.cpp",
+    "MipsCallLowering.cpp",
+    "MipsConstantIslandPass.cpp",
+    "MipsDelaySlotFiller.cpp",
+    "MipsExpandPseudo.cpp",
+    "MipsFastISel.cpp",
+    "MipsFrameLowering.cpp",
+    "MipsISelDAGToDAG.cpp",
+    "MipsISelLowering.cpp",
+    "MipsInstrInfo.cpp",
+    "MipsInstructionSelector.cpp",
+    "MipsLegalizerInfo.cpp",
+    "MipsMCInstLower.cpp",
+    "MipsMachineFunction.cpp",
+    "MipsModuleISelDAGToDAG.cpp",
+    "MipsOptimizePICCall.cpp",
+    "MipsOs16.cpp",
+    "MipsPreLegalizerCombiner.cpp",
+    "MipsRegisterBankInfo.cpp",
+    "MipsRegisterInfo.cpp",
+    "MipsSEFrameLowering.cpp",
+    "MipsSEISelDAGToDAG.cpp",
+    "MipsSEISelLowering.cpp",
+    "MipsSEInstrInfo.cpp",
+    "MipsSERegisterInfo.cpp",
+    "MipsSubtarget.cpp",
+    "MipsTargetMachine.cpp",
+    "MipsTargetObjectFile.cpp",
+  ]
+}
+
+# This is a bit different from most build files: Due to this group
+# having the directory's name, "//llvm/lib/Target/Mips" will refer to this
+# target, which pulls in the code in this directory *and all subdirectories*.
+# For most other directories, "//llvm/lib/Foo" only pulls in the code directly
+# in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this
+# different behavior.
+group("Mips") {
+  deps = [
+    ":LLVMMipsCodeGen",
+    "AsmParser",
+    "Disassembler",
+    "MCTargetDesc",
+    "TargetInfo",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/Mips/Disassembler/BUILD.gn

@@ -0,0 +1,22 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("MipsGenDisassemblerTables") {
+  visibility = [ ":Disassembler" ]
+  args = [ "-gen-disassembler" ]
+  td_file = "../Mips.td"
+}
+
+static_library("Disassembler") {
+  output_name = "LLVMMipsDisassembler"
+  deps = [
+    ":MipsGenDisassemblerTables",
+    "//llvm/lib/MC/MCDisassembler",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/Mips/MCTargetDesc",
+    "//llvm/lib/Target/Mips/TargetInfo",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "MipsDisassembler.cpp",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn

@@ -0,0 +1,76 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("MipsGenAsmWriter") {
+  visibility = [ ":MCTargetDesc" ]
+  args = [ "-gen-asm-writer" ]
+  td_file = "../Mips.td"
+}
+
+tablegen("MipsGenInstrInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-instr-info" ]
+  td_file = "../Mips.td"
+}
+
+tablegen("MipsGenMCCodeEmitter") {
+  visibility = [ ":MCTargetDesc" ]
+  args = [ "-gen-emitter" ]
+  td_file = "../Mips.td"
+}
+
+tablegen("MipsGenRegisterInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-register-info" ]
+  td_file = "../Mips.td"
+}
+
+tablegen("MipsGenSubtargetInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-subtarget" ]
+  td_file = "../Mips.td"
+}
+
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
+group("tablegen") {
+  visibility = [
+    ":MCTargetDesc",
+    "../TargetInfo",
+  ]
+  public_deps = [
+    ":MipsGenInstrInfo",
+    ":MipsGenRegisterInfo",
+    ":MipsGenSubtargetInfo",
+  ]
+}
+
+static_library("MCTargetDesc") {
+  output_name = "LLVMMipsDesc"
+  public_deps = [
+    ":tablegen",
+  ]
+  deps = [
+    ":MipsGenAsmWriter",
+    ":MipsGenMCCodeEmitter",
+    "//llvm/lib/MC",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/Mips/TargetInfo",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "MipsABIFlagsSection.cpp",
+    "MipsABIInfo.cpp",
+    "MipsAsmBackend.cpp",
+    "MipsELFObjectWriter.cpp",
+    "MipsELFStreamer.cpp",
+    "MipsInstPrinter.cpp",
+    "MipsMCAsmInfo.cpp",
+    "MipsMCCodeEmitter.cpp",
+    "MipsMCExpr.cpp",
+    "MipsMCTargetDesc.cpp",
+    "MipsNaClELFStreamer.cpp",
+    "MipsOptionRecord.cpp",
+    "MipsTargetStreamer.cpp",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/Mips/TargetInfo/BUILD.gn

@@ -0,0 +1,10 @@
+static_library("TargetInfo") {
+  output_name = "LLVMMipsInfo"
+  deps = [
+    "//llvm/lib/Support",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "MipsTargetInfo.cpp",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/targets.gni

@@ -25,6 +25,7 @@ if (llvm_targets_to_build == "host") {
     "BPF",
     "Hexagon",
     "Lanai",
+    "Mips",
     "PowerPC",
     "Sparc",
     "WebAssembly",
@@ -51,6 +52,8 @@ foreach(target, llvm_targets_to_build) {
     # Nothing to do.
   } else if (target == "Lanai") {
     # Nothing to do.
+  } else if (target == "Mips") {
+    # Nothing to do.
   } else if (target == "PowerPC") {
     llvm_build_PowerPC = true
   } else if (target == "RISCV") {