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fix an f32/f64 type mismatch

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23587 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-02 06:37:13 +00:00
parent 14765be0bc
commit 7c0d664c21
1 changed files with 6 additions and 2 deletions
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8
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -130,13 +130,17 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
default: assert(0 && "Wasn't expecting to be able to lower this!"); default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FP_TO_SINT: { case ISD::FP_TO_SINT: {
assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
SDOperand Src = Op.getOperand(0);
if (Src.getValueType() == MVT::f32)
Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
switch (Op.getValueType()) { switch (Op.getValueType()) {
default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
case MVT::i32: case MVT::i32:
Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Op.getOperand(0)); Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
break; break;
case MVT::i64: case MVT::i64:
Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Op.getOperand(0)); Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
break; break;
} }