RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2026-07-19 23:23:38 -04:00
Code Issues Packages Projects Releases 10 Wiki Activity

[AVR] Fix the testsuite after '%' changed to '$' in MIR

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324583 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dylan McKay
2018-02-08 09:17:11 +00:00
parent ee765a1d8f
commit 80d11db652
40 changed files with 119 additions and 119 deletions
Download Patch File Download Diff File Expand all files Collapse all files
test/CodeGen/AVR/pseudo/ADCWRdRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_adcwrdrr
; CHECK: %r14 = ADCRdRr %r14, %r20, implicit-def %sreg, implicit %sreg
; CHECK-LABEL: %r15 = ADCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
; CHECK: $r14 = ADCRdRr $r14, $r20, implicit-def $sreg, implicit $sreg
; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
%r15r14 = ADCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
$r15r14 = ADCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
...
test/CodeGen/AVR/pseudo/ADDWRdRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_addwrdrr
; CHECK: %r14 = ADDRdRr %r14, %r20, implicit-def %sreg
; CHECK-LABEL: %r15 = ADCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
; CHECK: $r14 = ADDRdRr $r14, $r20, implicit-def $sreg
; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
%r15r14 = ADDWRdRr %r15r14, %r21r20, implicit-def %sreg
$r15r14 = ADDWRdRr $r15r14, $r21r20, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/ANDIWRdK.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_andiwrdrr
; CHECK: %r16 = ANDIRdK %r16, 175, implicit-def dead %sreg
; CHECK-NEXT: %r17 = ANDIRdK %r17, 250, implicit-def %sreg
; CHECK: $r16 = ANDIRdK $r16, 175, implicit-def dead $sreg
; CHECK-NEXT: $r17 = ANDIRdK $r17, 250, implicit-def $sreg
%r17r16 = ANDIWRdK %r17r16, 64175, implicit-def %sreg
$r17r16 = ANDIWRdK $r17r16, 64175, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/ANDWRdRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_andwrdrr
; CHECK: %r14 = ANDRdRr %r14, %r20, implicit-def dead %sreg
; CHECK-NEXT: %r15 = ANDRdRr %r15, %r21, implicit-def %sreg
; CHECK: $r14 = ANDRdRr $r14, $r20, implicit-def dead $sreg
; CHECK-NEXT: $r15 = ANDRdRr $r15, $r21, implicit-def $sreg
%r15r14 = ANDWRdRr %r15r14, %r21r20, implicit-def %sreg
$r15r14 = ANDWRdRr $r15r14, $r21r20, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/ASRWRd.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: %r15 = ASRRd %r15, implicit-def %sreg
; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg
; CHECK: $r15 = ASRRd $r15, implicit-def $sreg
; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
%r15r14 = ASRWRd %r15r14, implicit-def %sreg
$r15r14 = ASRWRd $r15r14, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/COMWRd.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_comwrd
; CHECK: %r14 = COMRd %r14, implicit-def dead %sreg
; CHECK-NEXT: %r15 = COMRd %r15, implicit-def %sreg
; CHECK: $r14 = COMRd $r14, implicit-def dead $sreg
; CHECK-NEXT: $r15 = COMRd $r15, implicit-def $sreg
%r15r14 = COMWRd %r15r14, implicit-def %sreg
$r15r14 = COMWRd $r15r14, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/CPCWRdRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_cpcwrdrr
; CHECK: CPCRdRr %r20, %r22, implicit-def %sreg, implicit killed %sreg
; CHECK-NEXT: CPCRdRr %r21, %r23, implicit-def %sreg, implicit killed %sreg
; CHECK: CPCRdRr $r20, $r22, implicit-def $sreg, implicit killed $sreg
; CHECK-NEXT: CPCRdRr $r21, $r23, implicit-def $sreg, implicit killed $sreg
CPCWRdRr %r21r20, %r23r22, implicit-def %sreg, implicit %sreg
CPCWRdRr $r21r20, $r23r22, implicit-def $sreg, implicit $sreg
...
test/CodeGen/AVR/pseudo/CPWRdRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_cpwrdrr
; CHECK: CPRdRr %r14, %r20, implicit-def %sreg
; CHECK-NEXT: CPCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
; CHECK: CPRdRr $r14, $r20, implicit-def $sreg
; CHECK-NEXT: CPCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
CPWRdRr %r15r14, %r21r20, implicit-def %sreg
CPWRdRr $r15r14, $r21r20, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/EORWRdRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_eorwrdrr
; CHECK: %r14 = EORRdRr %r14, %r20, implicit-def dead %sreg
; CHECK-NEXT: %r15 = EORRdRr %r15, %r21, implicit-def %sreg
; CHECK: $r14 = EORRdRr $r14, $r20, implicit-def dead $sreg
; CHECK-NEXT: $r15 = EORRdRr $r15, $r21, implicit-def $sreg
%r15r14 = EORWRdRr %r15r14, %r21r20, implicit-def %sreg
$r15r14 = EORWRdRr $r15r14, $r21r20, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/FRMIDX.mir
+1 -1
View File
@@ -21,5 +21,5 @@ body: |
; CHECK-LABEL: test
%r29r28 = FRMIDX %r31r30, 0, implicit-def %sreg
$r29r28 = FRMIDX $r31r30, 0, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/INWRdA.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: %r14 = INRdA 31
; CHECK-NEXT: %r15 = INRdA 32
; CHECK: $r14 = INRdA 31
; CHECK-NEXT: $r15 = INRdA 32
%r15r14 = INWRdA 31
$r15r14 = INWRdA 31
...
test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir
+1 -1
View File
@@ -31,5 +31,5 @@ body: |
; CHECK-NEXT: mov r31, [[SCRATCH]]
; CHECK-NEXT: pop r30
early-clobber %r31r30 = LDDWRdPtrQ undef %r31r30, 10
early-clobber $r31r30 = LDDWRdPtrQ undef $r31r30, 10
...
test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
+1 -1
View File
@@ -21,5 +21,5 @@ body: |
; CHECK: ldd r30, Y+10
; CHECK-NEXT: ldd r31, Y+11
early-clobber %r31r30 = LDDWRdPtrQ undef %r29r28, 10
early-clobber $r31r30 = LDDWRdPtrQ undef $r29r28, 10
...
test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
+1 -1
View File
@@ -21,5 +21,5 @@ body: |
; CHECK: ldd r30, Y+1
; CHECK-NEXT: ldd r31, Y+2
early-clobber %r31r30 = LDDWRdYQ undef %r29r28, 1
early-clobber $r31r30 = LDDWRdYQ undef $r29r28, 1
...
test/CodeGen/AVR/pseudo/LDIWRdK.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldiwrdrr
; CHECK: %r30 = LDIRdK 255
; CHECK-NEXT: %r31 = LDIRdK 9
; CHECK: $r30 = LDIRdK 255
; CHECK-NEXT: $r31 = LDIRdK 9
%r31r30 = LDIWRdK 2559
$r31r30 = LDIWRdK 2559
...
test/CodeGen/AVR/pseudo/LDSWRdK.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldswrdrr
; CHECK: %r30 = LDSRdK 2559
; CHECK-NEXT: %r31 = LDSRdK 2560
; CHECK: $r30 = LDSRdK 2559
; CHECK-NEXT: $r31 = LDSRdK 2560
%r31r30 = LDSWRdK 2559
$r31r30 = LDSWRdK 2559
...
test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
+1 -1
View File
@@ -24,6 +24,6 @@ body: |
; CHECK-NEXT: mov r31, [[SCRATCH]]
; CHECK-NEXT: pop r30
early-clobber %r31r30 = LDWRdPtr undef %r31r30
early-clobber $r31r30 = LDWRdPtr undef $r31r30
...
test/CodeGen/AVR/pseudo/LDWRdPtr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldwrdptr
; CHECK: %r0, %r31r30 = LDRdPtrPi %r31r30
; CHECK-NEXT: %r1 = LDRdPtr %r31r30
; CHECK: $r0, $r31r30 = LDRdPtrPi $r31r30
; CHECK-NEXT: $r1 = LDRdPtr $r31r30
%r1r0 = LDWRdPtr %r31r30
$r1r0 = LDWRdPtr $r31r30
...
test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldwrdptrpd
; CHECK: early-clobber %r1, %r31r30 = LDRdPtrPd killed %r31r30
; CHECK-NEXT: early-clobber %r0, %r31r30 = LDRdPtrPd killed %r31r30
; CHECK: early-clobber $r1, $r31r30 = LDRdPtrPd killed $r31r30
; CHECK-NEXT: early-clobber $r0, $r31r30 = LDRdPtrPd killed $r31r30
%r1r0, %r31r30 = LDWRdPtrPd %r31r30
$r1r0, $r31r30 = LDWRdPtrPd $r31r30
...
test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldwrdptrpi
; CHECK: early-clobber %r0, %r31r30 = LDRdPtrPi killed %r31r30
; CHECK-NEXT: early-clobber %r1, %r31r30 = LDRdPtrPi killed %r31r30
; CHECK: early-clobber $r0, $r31r30 = LDRdPtrPi killed $r31r30
; CHECK-NEXT: early-clobber $r1, $r31r30 = LDRdPtrPi killed $r31r30
%r1r0, %r31r30 = LDWRdPtrPi %r31r30
$r1r0, $r31r30 = LDWRdPtrPi $r31r30
...
test/CodeGen/AVR/pseudo/LSLWRd.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: %r14 = LSLRd %r14, implicit-def %sreg
; CHECK-NEXT: %r15 = ROLRd %r15, implicit-def %sreg, implicit killed %sreg
; CHECK: $r14 = LSLRd $r14, implicit-def $sreg
; CHECK-NEXT: $r15 = ROLRd $r15, implicit-def $sreg, implicit killed $sreg
%r15r14 = LSLWRd %r15r14, implicit-def %sreg
$r15r14 = LSLWRd $r15r14, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/LSRWRd.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: %r15 = LSRRd %r15, implicit-def %sreg
; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg
; CHECK: $r15 = LSRRd $r15, implicit-def $sreg
; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
%r15r14 = LSRWRd %r15r14, implicit-def %sreg
$r15r14 = LSRWRd $r15r14, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/ORIWRdK.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_oriwrdrr
; CHECK: %r20 = ORIRdK %r20, 175, implicit-def dead %sreg
; CHECK-NEXT: %r21 = ORIRdK %r21, 250, implicit-def %sreg
; CHECK: $r20 = ORIRdK $r20, 175, implicit-def dead $sreg
; CHECK-NEXT: $r21 = ORIRdK $r21, 250, implicit-def $sreg
%r21r20 = ORIWRdK %r21r20, 64175, implicit-def %sreg
$r21r20 = ORIWRdK $r21r20, 64175, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/ORWRdRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_orwrdrr
; CHECK: %r14 = ORRdRr %r14, %r20, implicit-def dead %sreg
; CHECK-NEXT: %r15 = ORRdRr %r15, %r21, implicit-def %sreg
; CHECK: $r14 = ORRdRr $r14, $r20, implicit-def dead $sreg
; CHECK-NEXT: $r15 = ORRdRr $r15, $r21, implicit-def $sreg
%r15r14 = ORWRdRr %r15r14, %r21r20, implicit-def %sreg
$r15r14 = ORWRdRr $r15r14, $r21r20, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/OUTWARr.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: OUTARr 32, %r15
; CHECK-NEXT: OUTARr 31, %r14
; CHECK: OUTARr 32, $r15
; CHECK-NEXT: OUTARr 31, $r14
OUTWARr 31, %r15r14
OUTWARr 31, $r15r14
...
test/CodeGen/AVR/pseudo/POPWRd.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: %r29 = POPRd implicit-def %sp, implicit %sp
; CHECK-LABEL: %r28 = POPRd implicit-def %sp, implicit %sp
; CHECK: $r29 = POPRd implicit-def $sp, implicit $sp
; CHECK-LABEL: $r28 = POPRd implicit-def $sp, implicit $sp
%r29r28 = POPWRd implicit-def %sp, implicit %sp
$r29r28 = POPWRd implicit-def $sp, implicit $sp
...
test/CodeGen/AVR/pseudo/PUSHWRr.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: PUSHRr %r28, implicit-def %sp, implicit %sp
; CHECK-NEXT: PUSHRr %r29, implicit-def %sp, implicit %sp
; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
PUSHWRr %r29r28, implicit-def %sp, implicit %sp
PUSHWRr $r29r28, implicit-def $sp, implicit $sp
...
test/CodeGen/AVR/pseudo/SBCIWRdK.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_sbciwrdk
; CHECK: %r20 = SBCIRdK %r20, 175, implicit-def %sreg, implicit killed %sreg
; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
; CHECK: $r20 = SBCIRdK $r20, 175, implicit-def $sreg, implicit killed $sreg
; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
%r21r20 = SBCIWRdK %r21r20, 64175, implicit-def %sreg, implicit %sreg
$r21r20 = SBCIWRdK $r21r20, 64175, implicit-def $sreg, implicit $sreg
...
test/CodeGen/AVR/pseudo/SBCWRdRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_sbcwrdrr
; CHECK: %r14 = SBCRdRr %r14, %r20, implicit-def %sreg
; CHECK-NEXT: %r15 = SBCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
; CHECK: $r14 = SBCRdRr $r14, $r20, implicit-def $sreg
; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
%r15r14 = SBCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
$r15r14 = SBCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
...
test/CodeGen/AVR/pseudo/SEXT.mir
+5 -5
View File
@@ -15,10 +15,10 @@ body: |
; CHECK-LABEL: test
; CHECK: %r14 = MOVRdRr %r31
; CHECK-NEXT: %r15 = MOVRdRr %r31
; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg
; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg
; CHECK: $r14 = MOVRdRr $r31
; CHECK-NEXT: $r15 = MOVRdRr $r31
; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
%r15r14 = SEXT %r31, implicit-def %sreg
$r15r14 = SEXT $r31, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: STDPtrQRr %r29r28, 10, %r0
; CHECK-NEXT: STDPtrQRr %r29r28, 11, %r1
; CHECK: STDPtrQRr $r29r28, 10, $r0
; CHECK-NEXT: STDPtrQRr $r29r28, 11, $r1
STDWPtrQRr %r29r28, 10, %r1r0
STDWPtrQRr $r29r28, 10, $r1r0
...
test/CodeGen/AVR/pseudo/STSWKRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_stswkrr
; CHECK: STSKRr 2560, %r31
; CHECK-NEXT: STSKRr 2559, %r30
; CHECK: STSKRr 2560, $r31
; CHECK-NEXT: STSKRr 2559, $r30
STSWKRr 2559, %r31r30
STSWKRr 2559, $r31r30
...
test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r29, 52
; CHECK-NEXT: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r28, 52
; CHECK: early-clobber $r31r30 = STPtrPdRr killed $r31r30, $r29, 52
; CHECK-NEXT: early-clobber $r31r30 = STPtrPdRr killed $r31r30, $r28, 52
%r31r30 = STWPtrPdRr %r31r30, %r29r28, 52
$r31r30 = STWPtrPdRr $r31r30, $r29r28, 52
...
test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
+3 -3
View File
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
; CHECK: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r28, 52
; CHECK-NEXT: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r29, 52
; CHECK: early-clobber $r31r30 = STPtrPiRr killed $r31r30, $r28, 52
; CHECK-NEXT: early-clobber $r31r30 = STPtrPiRr killed $r31r30, $r29, 52
%r31r30 = STWPtrPiRr %r31r30, %r29r28, 52
$r31r30 = STWPtrPiRr $r31r30, $r29r28, 52
...
test/CodeGen/AVR/pseudo/STWPtrRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_stwptrrr
; CHECK: STPtrRr %r31r30, %r16
; CHECK-NEXT: STDPtrQRr %r31r30, 1, %r17
; CHECK: STPtrRr $r31r30, $r16
; CHECK-NEXT: STDPtrQRr $r31r30, 1, $r17
STWPtrRr %r31r30, %r17r16
STWPtrRr $r31r30, $r17r16
...
test/CodeGen/AVR/pseudo/SUBIWRdK.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_subiwrdrr
; CHECK: %r20 = SUBIRdK %r20, 175, implicit-def %sreg
; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
; CHECK: $r20 = SUBIRdK $r20, 175, implicit-def $sreg
; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
%r21r20 = SUBIWRdK %r21r20, 64175, implicit-def %sreg
$r21r20 = SUBIWRdK $r21r20, 64175, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/SUBWRdRr.mir
+3 -3
View File
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_subwrdrr
; CHECK: %r14 = SUBRdRr %r14, %r20, implicit-def %sreg
; CHECK-NEXT: %r15 = SBCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
; CHECK: $r14 = SUBRdRr $r14, $r20, implicit-def $sreg
; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
%r15r14 = SUBWRdRr %r15r14, %r21r20, implicit-def %sreg
$r15r14 = SUBWRdRr $r15r14, $r21r20, implicit-def $sreg
...
test/CodeGen/AVR/pseudo/ZEXT.mir
+5 -5
View File
@@ -15,10 +15,10 @@ body: |
; CHECK-LABEL: test
; CHECK: %r14 = MOVRdRr %r31
; CHECK-NEXT: %r15 = MOVRdRr %r31
; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg
; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg
; CHECK: $r14 = MOVRdRr $r31
; CHECK-NEXT: $r15 = MOVRdRr $r31
; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
%r15r14 = SEXT %r31, implicit-def %sreg
$r15r14 = SEXT $r31, implicit-def $sreg
...
test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
+9 -9
View File
@@ -16,16 +16,16 @@ body: |
; CHECK-LABEL: test
; We shouldn't expand things which already have 6-bit imms.
; CHECK: STDWPtrQRr %r29r28, 63, %r1r0
STDWPtrQRr %r29r28, 63, %r1r0
; CHECK: STDWPtrQRr $r29r28, 63, $r1r0
STDWPtrQRr $r29r28, 63, $r1r0
; We shouldn't expand things which already have 6-bit imms.
; CHECK-NEXT: STDWPtrQRr %r29r28, 0, %r1r0
STDWPtrQRr %r29r28, 0, %r1r0
; CHECK-NEXT: STDWPtrQRr $r29r28, 0, $r1r0
STDWPtrQRr $r29r28, 0, $r1r0
; CHECK-NEXT: PUSHWRr %r29r28, implicit-def %sp, implicit %sp
; CHECK-NEXT: %r29r28 = SBCIWRdK %r29r28, -64, implicit-def %sreg, implicit %sreg
; CHECK-NEXT: STWPtrRr %r29r28, %r1r0
; CHECK-NEXT: POPWRd %r29r28, implicit-def %sp, implicit %sp
STDWPtrQRr %r29r28, 64, %r1r0
; CHECK-NEXT: PUSHWRr $r29r28, implicit-def $sp, implicit $sp
; CHECK-NEXT: $r29r28 = SBCIWRdK $r29r28, -64, implicit-def $sreg, implicit $sreg
; CHECK-NEXT: STWPtrRr $r29r28, $r1r0
; CHECK-NEXT: POPWRd $r29r28, implicit-def $sp, implicit $sp
STDWPtrQRr $r29r28, 64, $r1r0
...
test/CodeGen/AVR/select-must-add-unconditional-jump.ll
+2 -2
View File
@@ -49,10 +49,10 @@ dead:
; basic block containing `select` needs to contain explicit jumps to
; both successors.
; CHECK: %bb.2.finish:
; CHECK: bb.2.finish:
; CHECK: BREQk [[BRANCHED:%bb.[0-9]+]]
; CHECK: RJMPk [[DIRECT:%bb.[0-9]+]]
; CHECK: Successors according to CFG
; CHECK-SAME-DAG: {{.*}}[[BRANCHED]]
; CHECK-SAME-DAG: {{.*}}[[DIRECT]]
; CHECK: %bb.3.dead:
; CHECK: bb.3.dead: