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[X86][Btver2] Improved latency/throughput model for scalar int-to-float conversions.

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Account for bypass delays when computing the latency of scalar int-to-float
conversions.
On Jaguar we need to account for an extra 6cy latency (see AMD fam16h SOG).
This patch also fixes the number of micropcodes for the register-memory variants
of scalar int-to-float conversions.

Differential Revision: https://reviews.llvm.org/D57148


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352518 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
2019-01-29 16:47:27 +00:00
parent 6887626c42
commit 8f2bb54a22
9 changed files with 66 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/Target/X86/X86InstrAVX512.td
+3 -3
View File
@@ -7508,7 +7508,7 @@ multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, X86FoldableSchedWrite sched
def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
(ins DstVT.FRC:$src1, SrcRC:$src),
!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
EVEX_4V, Sched<[sched]>;
EVEX_4V, Sched<[sched, ReadDefault, ReadInt2Fpu]>;
let mayLoad = 1 in
def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
(ins DstVT.FRC:$src1, x86memop:$src),
@@ -7523,7 +7523,7 @@ multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, X86FoldableSchedWrite sched
(OpNode (DstVT.VT DstVT.RC:$src1),
SrcRC:$src2,
(i32 FROUND_CURRENT)))]>,
EVEX_4V, Sched<[sched]>;
EVEX_4V, Sched<[sched, ReadDefault, ReadInt2Fpu]>;
def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
(ins DstVT.RC:$src1, x86memop:$src2),
@@ -7547,7 +7547,7 @@ multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode,
(OpNode (DstVT.VT DstVT.RC:$src1),
SrcRC:$src2,
(i32 imm:$rc)))]>,
EVEX_4V, EVEX_B, EVEX_RC, Sched<[sched]>;
EVEX_4V, EVEX_B, EVEX_RC, Sched<[sched, ReadDefault, ReadInt2Fpu]>;
}
multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode,
lib/Target/X86/X86InstrSSE.td
+9 -8
View File
@@ -846,10 +846,11 @@ let Constraints = "$src1 = $dst" in {
multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
string asm, X86FoldableSchedWrite sched> {
string asm, X86FoldableSchedWrite sched,
SchedRead Int2Fpu = ReadDefault> {
def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
[(set DstRC:$dst, (OpNode SrcRC:$src))]>,
Sched<[sched]>;
Sched<[sched, Int2Fpu]>;
def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
[(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>,
Sched<[sched.Folded]>;
@@ -876,7 +877,7 @@ multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
let hasSideEffects = 0, Predicates = [UseAVX] in {
def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Sched<[sched]>;
Sched<[sched, ReadDefault, ReadInt2Fpu]>;
let mayLoad = 1 in
def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
(ins DstRC:$src1, x86memop:$src),
@@ -972,16 +973,16 @@ defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
WriteCvtSD2I>, XD, REX_W;
defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
"cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
WriteCvtI2SS>, XS;
WriteCvtI2SS, ReadInt2Fpu>, XS;
defm CVTSI642SS : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
"cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
WriteCvtI2SS>, XS, REX_W;
WriteCvtI2SS, ReadInt2Fpu>, XS, REX_W;
defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
"cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
WriteCvtI2SD>, XD;
WriteCvtI2SD, ReadInt2Fpu>, XD;
defm CVTSI642SD : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
"cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
WriteCvtI2SD>, XD, REX_W;
WriteCvtI2SD, ReadInt2Fpu>, XD, REX_W;
def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
(CVTTSS2SIrr GR32:$dst, FR32:$src), 0, "att">;
@@ -1031,7 +1032,7 @@ let hasSideEffects = 0 in {
!if(Is2Addr,
!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
[]>, Sched<[sched]>;
[]>, Sched<[sched, ReadDefault, ReadInt2Fpu]>;
let mayLoad = 1 in
def rm_Int : SI<opc, MRMSrcMem, (outs DstRC:$dst),
(ins DstRC:$src1, x86memop:$src2),
lib/Target/X86/X86ScheduleBtVer2.td
+4 -3
View File
@@ -430,12 +430,13 @@ defm : JWriteResFpuPair<WriteCvtPD2I, [JFPU1, JSTC], 3, [1,1], 1>;
defm : JWriteResYMMPair<WriteCvtPD2IY, [JFPU1, JSTC, JFPX], 6, [2,2,4], 3>;
defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
// FIXME: f+3 ST, LD+STC latency
defm : JWriteResFpuPair<WriteCvtI2SS, [JFPU1, JSTC], 9, [1,1], 2>;
defm : X86WriteRes<WriteCvtI2SS, [JFPU1, JSTC], 4, [1,1], 2>;
defm : X86WriteRes<WriteCvtI2SSLd, [JLAGU, JFPU1, JSTC], 9, [1,1,1], 1>;
defm : JWriteResFpuPair<WriteCvtI2PS, [JFPU1, JSTC], 3, [1,1], 1>;
defm : JWriteResYMMPair<WriteCvtI2PSY, [JFPU1, JSTC], 3, [2,2], 2>;
defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
defm : JWriteResFpuPair<WriteCvtI2SD, [JFPU1, JSTC], 9, [1,1], 2>;
defm : X86WriteRes<WriteCvtI2SD, [JFPU1, JSTC], 4, [1,1], 2>;
defm : X86WriteRes<WriteCvtI2SDLd, [JLAGU, JFPU1, JSTC], 9, [1,1,1], 1>;
defm : JWriteResFpuPair<WriteCvtI2PD, [JFPU1, JSTC], 3, [1,1], 1>;
defm : JWriteResYMMPair<WriteCvtI2PDY, [JFPU1, JSTC], 3, [2,2], 2>;
defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
test/CodeGen/X86/sse-schedule.ll
+8 -8
View File
@@ -1171,15 +1171,15 @@ define float @test_cvtsi2ss(i32 %a0, i32 *%a1) {
;
; BTVER2-SSE-LABEL: test_cvtsi2ss:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: cvtsi2ssl (%rsi), %xmm0 # sched: [14:1.00]
; BTVER2-SSE-NEXT: cvtsi2ssl %edi, %xmm1 # sched: [9:1.00]
; BTVER2-SSE-NEXT: cvtsi2ssl (%rsi), %xmm0 # sched: [9:1.00]
; BTVER2-SSE-NEXT: cvtsi2ssl %edi, %xmm1 # sched: [10:1.00]
; BTVER2-SSE-NEXT: addss %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_cvtsi2ss:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [9:1.00]
; BTVER2-NEXT: vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
; BTVER2-NEXT: vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [10:1.00]
; BTVER2-NEXT: vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; BTVER2-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -1311,15 +1311,15 @@ define float @test_cvtsi2ssq(i64 %a0, i64 *%a1) {
;
; BTVER2-SSE-LABEL: test_cvtsi2ssq:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: cvtsi2ssq (%rsi), %xmm0 # sched: [14:1.00]
; BTVER2-SSE-NEXT: cvtsi2ssq %rdi, %xmm1 # sched: [9:1.00]
; BTVER2-SSE-NEXT: cvtsi2ssq (%rsi), %xmm0 # sched: [9:1.00]
; BTVER2-SSE-NEXT: cvtsi2ssq %rdi, %xmm1 # sched: [10:1.00]
; BTVER2-SSE-NEXT: addss %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_cvtsi2ssq:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [9:1.00]
; BTVER2-NEXT: vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
; BTVER2-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [10:1.00]
; BTVER2-NEXT: vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; BTVER2-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
test/CodeGen/X86/sse2-schedule.ll
+8 -8
View File
@@ -2608,15 +2608,15 @@ define double @test_cvtsi2sd(i32 %a0, i32 *%a1) {
;
; BTVER2-SSE-LABEL: test_cvtsi2sd:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: cvtsi2sdl (%rsi), %xmm0 # sched: [14:1.00]
; BTVER2-SSE-NEXT: cvtsi2sdl %edi, %xmm1 # sched: [9:1.00]
; BTVER2-SSE-NEXT: cvtsi2sdl (%rsi), %xmm0 # sched: [9:1.00]
; BTVER2-SSE-NEXT: cvtsi2sdl %edi, %xmm1 # sched: [10:1.00]
; BTVER2-SSE-NEXT: addsd %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_cvtsi2sd:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [9:1.00]
; BTVER2-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
; BTVER2-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [10:1.00]
; BTVER2-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -2748,15 +2748,15 @@ define double @test_cvtsi2sdq(i64 %a0, i64 *%a1) {
;
; BTVER2-SSE-LABEL: test_cvtsi2sdq:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: cvtsi2sdq (%rsi), %xmm0 # sched: [14:1.00]
; BTVER2-SSE-NEXT: cvtsi2sdq %rdi, %xmm1 # sched: [9:1.00]
; BTVER2-SSE-NEXT: cvtsi2sdq (%rsi), %xmm0 # sched: [9:1.00]
; BTVER2-SSE-NEXT: cvtsi2sdq %rdi, %xmm1 # sched: [10:1.00]
; BTVER2-SSE-NEXT: addsd %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_cvtsi2sdq:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [9:1.00]
; BTVER2-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
; BTVER2-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [10:1.00]
; BTVER2-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-2.s
+18 -17
View File
@@ -1,7 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=500 < %s | FileCheck %s
# Throughput for all the code snippet below should tend to 1.00 IPC.
# Throughput for the AVX code snippets below should tend to 0.25 IPC.
# Throughput for the SSE code snippets below should tend to 1.00 IPC.
# LLVM-MCA-BEGIN
vcvtsi2ss %ecx, %xmm0, %xmm0
@@ -31,12 +32,12 @@ movq %rcx, %xmm0
# CHECK: Iterations: 500
# CHECK-NEXT: Instructions: 500
# CHECK-NEXT: Total Cycles: 4503
# CHECK-NEXT: Total Cycles: 2003
# CHECK-NEXT: Total uOps: 1000
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.22
# CHECK-NEXT: IPC: 0.11
# CHECK-NEXT: uOps Per Cycle: 0.50
# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info:
@@ -48,7 +49,7 @@ movq %rcx, %xmm0
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 9 1.00 vcvtsi2ssl %ecx, %xmm0, %xmm0
# CHECK-NEXT: 2 10 1.00 vcvtsi2ssl %ecx, %xmm0, %xmm0
# CHECK: Resources:
# CHECK-NEXT: [0] - JALU0
@@ -78,12 +79,12 @@ movq %rcx, %xmm0
# CHECK: Iterations: 500
# CHECK-NEXT: Instructions: 500
# CHECK-NEXT: Total Cycles: 4503
# CHECK-NEXT: Total Cycles: 2003
# CHECK-NEXT: Total uOps: 1000
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.22
# CHECK-NEXT: IPC: 0.11
# CHECK-NEXT: uOps Per Cycle: 0.50
# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info:
@@ -95,7 +96,7 @@ movq %rcx, %xmm0
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 9 1.00 vcvtsi2sdl %ecx, %xmm0, %xmm0
# CHECK-NEXT: 2 10 1.00 vcvtsi2sdl %ecx, %xmm0, %xmm0
# CHECK: Resources:
# CHECK-NEXT: [0] - JALU0
@@ -125,12 +126,12 @@ movq %rcx, %xmm0
# CHECK: Iterations: 500
# CHECK-NEXT: Instructions: 500
# CHECK-NEXT: Total Cycles: 511
# CHECK-NEXT: Total Cycles: 506
# CHECK-NEXT: Total uOps: 1000
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 1.96
# CHECK-NEXT: IPC: 0.98
# CHECK-NEXT: uOps Per Cycle: 1.98
# CHECK-NEXT: IPC: 0.99
# CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info:
@@ -142,7 +143,7 @@ movq %rcx, %xmm0
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 9 1.00 cvtsi2ssl %ecx, %xmm0
# CHECK-NEXT: 2 10 1.00 cvtsi2ssl %ecx, %xmm0
# CHECK: Resources:
# CHECK-NEXT: [0] - JALU0
@@ -172,12 +173,12 @@ movq %rcx, %xmm0
# CHECK: Iterations: 500
# CHECK-NEXT: Instructions: 500
# CHECK-NEXT: Total Cycles: 511
# CHECK-NEXT: Total Cycles: 506
# CHECK-NEXT: Total uOps: 1000
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 1.96
# CHECK-NEXT: IPC: 0.98
# CHECK-NEXT: uOps Per Cycle: 1.98
# CHECK-NEXT: IPC: 0.99
# CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info:
@@ -189,7 +190,7 @@ movq %rcx, %xmm0
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 9 1.00 cvtsi2sdl %ecx, %xmm0
# CHECK-NEXT: 2 10 1.00 cvtsi2sdl %ecx, %xmm0
# CHECK: Resources:
# CHECK-NEXT: [0] - JALU0
test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
+8 -8
View File
@@ -1144,14 +1144,14 @@ vzeroupper
# CHECK-NEXT: 2 12 1.00 * vcvtsd2si (%rax), %rcx
# CHECK-NEXT: 2 7 2.00 vcvtsd2ss %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 2 12 2.00 * vcvtsd2ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 9 1.00 vcvtsi2sdl %ecx, %xmm0, %xmm2
# CHECK-NEXT: 2 9 1.00 vcvtsi2sdq %rcx, %xmm0, %xmm2
# CHECK-NEXT: 2 14 1.00 * vcvtsi2sdl (%rax), %xmm0, %xmm2
# CHECK-NEXT: 2 14 1.00 * vcvtsi2sdq (%rax), %xmm0, %xmm2
# CHECK-NEXT: 2 9 1.00 vcvtsi2ssl %ecx, %xmm0, %xmm2
# CHECK-NEXT: 2 9 1.00 vcvtsi2ssq %rcx, %xmm0, %xmm2
# CHECK-NEXT: 2 14 1.00 * vcvtsi2ssl (%rax), %xmm0, %xmm2
# CHECK-NEXT: 2 14 1.00 * vcvtsi2ssq (%rax), %xmm0, %xmm2
# CHECK-NEXT: 2 10 1.00 vcvtsi2sdl %ecx, %xmm0, %xmm2
# CHECK-NEXT: 2 10 1.00 vcvtsi2sdq %rcx, %xmm0, %xmm2
# CHECK-NEXT: 1 9 1.00 * vcvtsi2sdl (%rax), %xmm0, %xmm2
# CHECK-NEXT: 1 9 1.00 * vcvtsi2sdq (%rax), %xmm0, %xmm2
# CHECK-NEXT: 2 10 1.00 vcvtsi2ssl %ecx, %xmm0, %xmm2
# CHECK-NEXT: 2 10 1.00 vcvtsi2ssq %rcx, %xmm0, %xmm2
# CHECK-NEXT: 1 9 1.00 * vcvtsi2ssl (%rax), %xmm0, %xmm2
# CHECK-NEXT: 1 9 1.00 * vcvtsi2ssq (%rax), %xmm0, %xmm2
# CHECK-NEXT: 2 7 2.00 vcvtss2sd %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 2 12 2.00 * vcvtss2sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtss2si %xmm0, %ecx
test/tools/llvm-mca/X86/BtVer2/resources-sse1.s
+4 -4
View File
@@ -212,10 +212,10 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 1 8 1.00 * cvtpi2ps (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 cvtps2pi %xmm0, %mm2
# CHECK-NEXT: 1 8 1.00 * cvtps2pi (%rax), %mm2
# CHECK-NEXT: 2 9 1.00 cvtsi2ssl %ecx, %xmm2
# CHECK-NEXT: 2 9 1.00 cvtsi2ssq %rcx, %xmm2
# CHECK-NEXT: 2 14 1.00 * cvtsi2ssl (%rax), %xmm2
# CHECK-NEXT: 2 14 1.00 * cvtsi2ssl (%rax), %xmm2
# CHECK-NEXT: 2 10 1.00 cvtsi2ssl %ecx, %xmm2
# CHECK-NEXT: 2 10 1.00 cvtsi2ssq %rcx, %xmm2
# CHECK-NEXT: 1 9 1.00 * cvtsi2ssl (%rax), %xmm2
# CHECK-NEXT: 1 9 1.00 * cvtsi2ssl (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 cvtss2si %xmm0, %ecx
# CHECK-NEXT: 2 7 1.00 cvtss2si %xmm0, %rcx
# CHECK-NEXT: 2 12 1.00 * cvtss2si (%rax), %ecx
test/tools/llvm-mca/X86/BtVer2/resources-sse2.s
+4 -4
View File
@@ -444,10 +444,10 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: 2 12 1.00 * cvtsd2si (%rax), %rcx
# CHECK-NEXT: 2 7 2.00 cvtsd2ss %xmm0, %xmm2
# CHECK-NEXT: 2 12 2.00 * cvtsd2ss (%rax), %xmm2
# CHECK-NEXT: 2 9 1.00 cvtsi2sdl %ecx, %xmm2
# CHECK-NEXT: 2 9 1.00 cvtsi2sdq %rcx, %xmm2
# CHECK-NEXT: 2 14 1.00 * cvtsi2sdl (%rax), %xmm2
# CHECK-NEXT: 2 14 1.00 * cvtsi2sdl (%rax), %xmm2
# CHECK-NEXT: 2 10 1.00 cvtsi2sdl %ecx, %xmm2
# CHECK-NEXT: 2 10 1.00 cvtsi2sdq %rcx, %xmm2
# CHECK-NEXT: 1 9 1.00 * cvtsi2sdl (%rax), %xmm2
# CHECK-NEXT: 1 9 1.00 * cvtsi2sdl (%rax), %xmm2
# CHECK-NEXT: 2 7 2.00 cvtss2sd %xmm0, %xmm2
# CHECK-NEXT: 2 12 2.00 * cvtss2sd (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 cvttpd2dq %xmm0, %xmm2