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[X86] Add custom type legalization for v16i64->v16i8 truncate and v8i64->v8i8 truncate when v8i64 isn't legal
Summary: The default legalization for v16i64->v16i8 tries to create a multiple stage truncate concatenating after each stage and truncating again. But avx512 implements truncates with multiple uops. So it should be better to truncate all the way to the desired element size and then concatenate the pieces using unpckl instructions. This minimizes the number of 2 uop truncates. The unpcks are all single uop instructions. I tried to handle this by just custom splitting the v16i64->v16i8 shuffle. And hoped that the DAG combiner would leave the two halves in the state needed to make D68374 do the job for each half. This worked for the first half, but the second half got messed up. So I've implemented custom handling for v8i64->v8i8 when v8i64 needs to be split to produce the VTRUNCs directly. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68428 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373864 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
@@ -1763,6 +1763,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::TRUNCATE, MVT::v16i32, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v8i64, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom);
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}
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// We want to custom lower some of our intrinsics.
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@@ -19329,9 +19330,11 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
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assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
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"Invalid TRUNCATE operation");
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// If called by the legalizer just return.
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if (!DAG.getTargetLoweringInfo().isTypeLegal(InVT)) {
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if ((InVT == MVT::v8i64 || InVT == MVT::v16i32) && VT.is128BitVector()) {
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// If we're called by the type legalizer, handle a few cases.
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (!TLI.isTypeLegal(InVT)) {
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if ((InVT == MVT::v8i64 || InVT == MVT::v16i32 || InVT == MVT::v16i64) &&
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VT.is128BitVector()) {
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assert(Subtarget.hasVLX() && "Unexpected subtarget!");
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// The default behavior is to truncate one step, concatenate, and then
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// truncate the remainder. We'd rather produce two 64-bit results and
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@@ -27958,6 +27961,23 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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return;
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}
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}
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if (Subtarget.hasVLX() && InVT == MVT::v8i64 && VT == MVT::v8i8 &&
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getTypeAction(*DAG.getContext(), InVT) == TypeSplitVector &&
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isTypeLegal(MVT::v4i64)) {
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// Input needs to be split and output needs to widened. Let's use two
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// VTRUNCs, and shuffle their results together into the wider type.
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SDValue Lo, Hi;
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std::tie(Lo, Hi) = DAG.SplitVector(In, dl);
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Lo = DAG.getNode(X86ISD::VTRUNC, dl, MVT::v16i8, Lo);
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Hi = DAG.getNode(X86ISD::VTRUNC, dl, MVT::v16i8, Hi);
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SDValue Res = DAG.getVectorShuffle(MVT::v16i8, dl, Lo, Hi,
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{ 0, 1, 2, 3, 16, 17, 18, 19,
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-1, -1, -1, -1, -1, -1, -1, -1 });
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Results.push_back(Res);
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return;
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}
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return;
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}
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case ISD::ANY_EXTEND:
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@@ -797,14 +797,12 @@ define <16 x i8> @trunc_v16i64_v16i8(<16 x i64>* %x) nounwind "min-legal-vector-
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; CHECK-NEXT: vmovdqa 32(%rdi), %ymm1
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; CHECK-NEXT: vmovdqa 64(%rdi), %ymm2
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; CHECK-NEXT: vmovdqa 96(%rdi), %ymm3
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; CHECK-NEXT: vpmovqd %ymm2, %xmm2
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; CHECK-NEXT: vpmovqd %ymm3, %xmm3
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; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
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; CHECK-NEXT: vpmovdb %ymm2, %xmm2
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; CHECK-NEXT: vpmovqd %ymm0, %xmm0
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; CHECK-NEXT: vpmovqd %ymm1, %xmm1
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; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; CHECK-NEXT: vpmovdb %ymm0, %xmm0
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; CHECK-NEXT: vpmovqb %ymm3, %xmm3
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; CHECK-NEXT: vpmovqb %ymm2, %xmm2
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; CHECK-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
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; CHECK-NEXT: vpmovqb %ymm1, %xmm1
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; CHECK-NEXT: vpmovqb %ymm0, %xmm0
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; CHECK-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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@@ -829,24 +827,15 @@ define <16 x i8> @trunc_v16i32_v16i8(<16 x i32>* %x) nounwind "min-legal-vector-
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}
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define <8 x i8> @trunc_v8i64_v8i8(<8 x i64>* %x) nounwind "min-legal-vector-width"="256" {
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; CHECK-AVX512-LABEL: trunc_v8i64_v8i8:
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; CHECK-AVX512: # %bb.0:
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; CHECK-AVX512-NEXT: vmovdqa (%rdi), %ymm0
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; CHECK-AVX512-NEXT: vmovdqa 32(%rdi), %ymm1
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; CHECK-AVX512-NEXT: vpmovqb %ymm1, %xmm1
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; CHECK-AVX512-NEXT: vpmovqb %ymm0, %xmm0
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; CHECK-AVX512-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; CHECK-AVX512-NEXT: vzeroupper
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; CHECK-AVX512-NEXT: retq
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;
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; CHECK-VBMI-LABEL: trunc_v8i64_v8i8:
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; CHECK-VBMI: # %bb.0:
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; CHECK-VBMI-NEXT: vmovdqa (%rdi), %ymm1
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; CHECK-VBMI-NEXT: vpbroadcastq {{.*#+}} ymm0 = [4048780183313844224,4048780183313844224,4048780183313844224,4048780183313844224]
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; CHECK-VBMI-NEXT: vpermi2b 32(%rdi), %ymm1, %ymm0
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; CHECK-VBMI-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; CHECK-VBMI-NEXT: vzeroupper
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; CHECK-VBMI-NEXT: retq
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; CHECK-LABEL: trunc_v8i64_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovdqa (%rdi), %ymm0
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; CHECK-NEXT: vmovdqa 32(%rdi), %ymm1
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; CHECK-NEXT: vpmovqb %ymm1, %xmm1
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; CHECK-NEXT: vpmovqb %ymm0, %xmm0
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; CHECK-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%a = load <8 x i64>, <8 x i64>* %x
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%b = trunc <8 x i64> %a to <8 x i8>
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ret <8 x i8> %b
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@@ -2732,20 +2732,57 @@ define <16 x i8> @trunc_packus_v16i64_v16i8(<16 x i64> %a0) {
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: trunc_packus_v16i64_v16i8:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpbroadcastq {{.*#+}} zmm2 = [255,255,255,255,255,255,255,255]
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; AVX512-NEXT: vpminsq %zmm2, %zmm0, %zmm0
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; AVX512-NEXT: vpminsq %zmm2, %zmm1, %zmm1
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; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX512-NEXT: vpmaxsq %zmm2, %zmm1, %zmm1
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; AVX512-NEXT: vpmaxsq %zmm2, %zmm0, %zmm0
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; AVX512-NEXT: vpmovqd %zmm0, %ymm0
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; AVX512-NEXT: vpmovqd %zmm1, %ymm1
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; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512-NEXT: vpmovdb %zmm0, %xmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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; AVX512F-LABEL: trunc_packus_v16i64_v16i8:
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; AVX512F: # %bb.0:
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; AVX512F-NEXT: vpbroadcastq {{.*#+}} zmm2 = [255,255,255,255,255,255,255,255]
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; AVX512F-NEXT: vpminsq %zmm2, %zmm0, %zmm0
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; AVX512F-NEXT: vpminsq %zmm2, %zmm1, %zmm1
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; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX512F-NEXT: vpmaxsq %zmm2, %zmm1, %zmm1
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; AVX512F-NEXT: vpmaxsq %zmm2, %zmm0, %zmm0
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; AVX512F-NEXT: vpmovqd %zmm0, %ymm0
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; AVX512F-NEXT: vpmovqd %zmm1, %ymm1
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; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
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; AVX512F-NEXT: vzeroupper
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; AVX512F-NEXT: retq
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;
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; AVX512VL-LABEL: trunc_packus_v16i64_v16i8:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX512VL-NEXT: vpmaxsq %zmm2, %zmm1, %zmm1
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; AVX512VL-NEXT: vpmovusqb %zmm1, %xmm1
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; AVX512VL-NEXT: vpmaxsq %zmm2, %zmm0, %zmm0
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; AVX512VL-NEXT: vpmovusqb %zmm0, %xmm0
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; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX512VL-NEXT: vzeroupper
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; AVX512VL-NEXT: retq
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;
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; AVX512BW-LABEL: trunc_packus_v16i64_v16i8:
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; AVX512BW: # %bb.0:
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; AVX512BW-NEXT: vpbroadcastq {{.*#+}} zmm2 = [255,255,255,255,255,255,255,255]
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; AVX512BW-NEXT: vpminsq %zmm2, %zmm0, %zmm0
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; AVX512BW-NEXT: vpminsq %zmm2, %zmm1, %zmm1
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; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX512BW-NEXT: vpmaxsq %zmm2, %zmm1, %zmm1
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; AVX512BW-NEXT: vpmaxsq %zmm2, %zmm0, %zmm0
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; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0
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; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1
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; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512BW-NEXT: vpmovdb %zmm0, %xmm0
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: retq
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;
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; AVX512BWVL-LABEL: trunc_packus_v16i64_v16i8:
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; AVX512BWVL: # %bb.0:
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; AVX512BWVL-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX512BWVL-NEXT: vpmaxsq %zmm2, %zmm1, %zmm1
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; AVX512BWVL-NEXT: vpmovusqb %zmm1, %xmm1
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; AVX512BWVL-NEXT: vpmaxsq %zmm2, %zmm0, %zmm0
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; AVX512BWVL-NEXT: vpmovusqb %zmm0, %xmm0
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; AVX512BWVL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX512BWVL-NEXT: vzeroupper
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; AVX512BWVL-NEXT: retq
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%1 = icmp slt <16 x i64> %a0, <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
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%2 = select <16 x i1> %1, <16 x i64> %a0, <16 x i64> <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
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%3 = icmp sgt <16 x i64> %2, zeroinitializer
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@@ -2717,20 +2717,51 @@ define <16 x i8> @trunc_ssat_v16i64_v16i8(<16 x i64> %a0) {
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: trunc_ssat_v16i64_v16i8:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpbroadcastq {{.*#+}} zmm2 = [127,127,127,127,127,127,127,127]
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; AVX512-NEXT: vpminsq %zmm2, %zmm0, %zmm0
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; AVX512-NEXT: vpminsq %zmm2, %zmm1, %zmm1
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; AVX512-NEXT: vpbroadcastq {{.*#+}} zmm2 = [18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488]
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; AVX512-NEXT: vpmaxsq %zmm2, %zmm1, %zmm1
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; AVX512-NEXT: vpmaxsq %zmm2, %zmm0, %zmm0
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; AVX512-NEXT: vpmovqd %zmm0, %ymm0
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; AVX512-NEXT: vpmovqd %zmm1, %ymm1
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; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512-NEXT: vpmovdb %zmm0, %xmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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; AVX512F-LABEL: trunc_ssat_v16i64_v16i8:
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; AVX512F: # %bb.0:
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; AVX512F-NEXT: vpbroadcastq {{.*#+}} zmm2 = [127,127,127,127,127,127,127,127]
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; AVX512F-NEXT: vpminsq %zmm2, %zmm0, %zmm0
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; AVX512F-NEXT: vpminsq %zmm2, %zmm1, %zmm1
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; AVX512F-NEXT: vpbroadcastq {{.*#+}} zmm2 = [18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488]
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; AVX512F-NEXT: vpmaxsq %zmm2, %zmm1, %zmm1
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; AVX512F-NEXT: vpmaxsq %zmm2, %zmm0, %zmm0
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; AVX512F-NEXT: vpmovqd %zmm0, %ymm0
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; AVX512F-NEXT: vpmovqd %zmm1, %ymm1
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; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
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; AVX512F-NEXT: vzeroupper
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; AVX512F-NEXT: retq
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;
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; AVX512VL-LABEL: trunc_ssat_v16i64_v16i8:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vpmovsqb %zmm1, %xmm1
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; AVX512VL-NEXT: vpmovsqb %zmm0, %xmm0
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; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX512VL-NEXT: vzeroupper
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; AVX512VL-NEXT: retq
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;
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; AVX512BW-LABEL: trunc_ssat_v16i64_v16i8:
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; AVX512BW: # %bb.0:
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; AVX512BW-NEXT: vpbroadcastq {{.*#+}} zmm2 = [127,127,127,127,127,127,127,127]
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; AVX512BW-NEXT: vpminsq %zmm2, %zmm0, %zmm0
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; AVX512BW-NEXT: vpminsq %zmm2, %zmm1, %zmm1
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; AVX512BW-NEXT: vpbroadcastq {{.*#+}} zmm2 = [18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488,18446744073709551488]
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; AVX512BW-NEXT: vpmaxsq %zmm2, %zmm1, %zmm1
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; AVX512BW-NEXT: vpmaxsq %zmm2, %zmm0, %zmm0
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; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0
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; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1
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; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512BW-NEXT: vpmovdb %zmm0, %xmm0
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: retq
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;
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; AVX512BWVL-LABEL: trunc_ssat_v16i64_v16i8:
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; AVX512BWVL: # %bb.0:
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; AVX512BWVL-NEXT: vpmovsqb %zmm1, %xmm1
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; AVX512BWVL-NEXT: vpmovsqb %zmm0, %xmm0
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; AVX512BWVL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX512BWVL-NEXT: vzeroupper
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; AVX512BWVL-NEXT: retq
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%1 = icmp slt <16 x i64> %a0, <i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127>
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%2 = select <16 x i1> %1, <16 x i64> %a0, <16 x i64> <i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127, i64 127>
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%3 = icmp sgt <16 x i64> %2, <i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128, i64 -128>
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@@ -1842,17 +1842,45 @@ define <16 x i8> @trunc_usat_v16i64_v16i8(<16 x i64> %a0) {
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: trunc_usat_v16i64_v16i8:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpbroadcastq {{.*#+}} zmm2 = [255,255,255,255,255,255,255,255]
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; AVX512-NEXT: vpminuq %zmm2, %zmm1, %zmm1
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; AVX512-NEXT: vpminuq %zmm2, %zmm0, %zmm0
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; AVX512-NEXT: vpmovqd %zmm0, %ymm0
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; AVX512-NEXT: vpmovqd %zmm1, %ymm1
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; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512-NEXT: vpmovdb %zmm0, %xmm0
|
||||
; AVX512-NEXT: vzeroupper
|
||||
; AVX512-NEXT: retq
|
||||
; AVX512F-LABEL: trunc_usat_v16i64_v16i8:
|
||||
; AVX512F: # %bb.0:
|
||||
; AVX512F-NEXT: vpbroadcastq {{.*#+}} zmm2 = [255,255,255,255,255,255,255,255]
|
||||
; AVX512F-NEXT: vpminuq %zmm2, %zmm1, %zmm1
|
||||
; AVX512F-NEXT: vpminuq %zmm2, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vpmovqd %zmm0, %ymm0
|
||||
; AVX512F-NEXT: vpmovqd %zmm1, %ymm1
|
||||
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
|
||||
; AVX512F-NEXT: vzeroupper
|
||||
; AVX512F-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: trunc_usat_v16i64_v16i8:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpmovusqb %zmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpmovusqb %zmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX512VL-NEXT: vzeroupper
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
; AVX512BW-LABEL: trunc_usat_v16i64_v16i8:
|
||||
; AVX512BW: # %bb.0:
|
||||
; AVX512BW-NEXT: vpbroadcastq {{.*#+}} zmm2 = [255,255,255,255,255,255,255,255]
|
||||
; AVX512BW-NEXT: vpminuq %zmm2, %zmm1, %zmm1
|
||||
; AVX512BW-NEXT: vpminuq %zmm2, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0
|
||||
; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1
|
||||
; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: vpmovdb %zmm0, %xmm0
|
||||
; AVX512BW-NEXT: vzeroupper
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512BWVL-LABEL: trunc_usat_v16i64_v16i8:
|
||||
; AVX512BWVL: # %bb.0:
|
||||
; AVX512BWVL-NEXT: vpmovusqb %zmm1, %xmm1
|
||||
; AVX512BWVL-NEXT: vpmovusqb %zmm0, %xmm0
|
||||
; AVX512BWVL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX512BWVL-NEXT: vzeroupper
|
||||
; AVX512BWVL-NEXT: retq
|
||||
%1 = icmp ult <16 x i64> %a0, <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
|
||||
%2 = select <16 x i1> %1, <16 x i64> %a0, <16 x i64> <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
|
||||
%3 = trunc <16 x i64> %2 to <16 x i8>
|
||||
|
||||
Reference in New Issue
Block a user