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Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't

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forget to right shift the source by 32 first. rdar://9287902


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129556 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-04-15 01:31:00 +00:00
parent 188ce9c78b
commit 9eec66e604
2 changed files with 25 additions and 5 deletions
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5
lib/Target/ARM/ARMISelLowering.cpp
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@ -2952,7 +2952,10 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
DAG.getConstant(32, MVT::i32)); DAG.getConstant(32, MVT::i32));
} } else if (VT == MVT::f32)
Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
DAG.getConstant(32, MVT::i32));
Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);

25
test/CodeGen/ARM/fcopysign.ll
View File

@ -44,15 +44,32 @@ entry:
define i32 @test4() ssp { define i32 @test4() ssp {
entry: entry:
; SOFT: test4: ; SOFT: test4:
; SOFT: vcvt.f32.f64 s0, ; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
; SOFT: vmov.i32 [[REG4:(d[0-9]+)]], #0x80000000 ; SOFT: vcvt.f32.f64 s0, [[REG4]]
; SOFT: vbic [[REG5:(d[0-9]+)]], d0, [[REG4]] ; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
; SOFT: vorr d0, [[REG4]], [[REG5]] ; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
; SOFT: vbsl [[REG5]], [[REG4]], d0
%call80 = tail call double @copysign(double 1.000000e+00, double undef) %call80 = tail call double @copysign(double 1.000000e+00, double undef)
%conv81 = fptrunc double %call80 to float %conv81 = fptrunc double %call80 to float
%tmp88 = bitcast float %conv81 to i32 %tmp88 = bitcast float %conv81 to i32
ret i32 %tmp88 ret i32 %tmp88
} }
; rdar://9287902
define float @test5() nounwind {
entry:
; SOFT: test5:
; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
; SOFT: vbsl [[REG6]], [[REG7]],
%0 = tail call double (...)* @bar() nounwind
%1 = fptrunc double %0 to float
%2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
%3 = fadd float %1, %2
ret float %3
}
declare double @bar(...)
declare double @copysign(double, double) nounwind declare double @copysign(double, double) nounwind
declare float @copysignf(float, float) nounwind declare float @copysignf(float, float) nounwind