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[AMDGPU] Extend the SI Load/Store optimizer
Summary: Extend the SI Load/Store optimizer to merge MIMG load instructions. Handle different flavours of image_load and image_sample instructions. When the instructions of the same subclass differ only in dmask, merge them and update dmask accordingly. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374984 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Piotr Sobczak
@@ -97,6 +97,7 @@ enum InstClassEnum {
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S_BUFFER_LOAD_IMM,
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BUFFER_LOAD,
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BUFFER_STORE,
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MIMG,
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};
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enum RegisterEnum {
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@@ -105,6 +106,7 @@ enum RegisterEnum {
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SOFFSET = 0x4,
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VADDR = 0x8,
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ADDR = 0x10,
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SSAMP = 0x20,
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};
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class SILoadStoreOptimizer : public MachineFunctionPass {
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@@ -117,6 +119,8 @@ class SILoadStoreOptimizer : public MachineFunctionPass {
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unsigned Width0;
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unsigned Width1;
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unsigned BaseOff;
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unsigned DMask0;
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unsigned DMask1;
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InstClassEnum InstClass;
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bool GLC0;
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bool GLC1;
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@@ -205,6 +209,7 @@ private:
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AliasAnalysis *AA = nullptr;
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bool OptimizeAgain;
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static bool dmasksCanBeCombined(const CombineInfo &CI, const SIInstrInfo &TII);
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static bool offsetsCanBeCombined(CombineInfo &CI);
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static bool widthsFit(const GCNSubtarget &STM, const CombineInfo &CI);
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static unsigned getNewOpcode(const CombineInfo &CI);
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@@ -220,6 +225,7 @@ private:
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unsigned write2Opcode(unsigned EltSize) const;
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unsigned write2ST64Opcode(unsigned EltSize) const;
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MachineBasicBlock::iterator mergeWrite2Pair(CombineInfo &CI);
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MachineBasicBlock::iterator mergeImagePair(CombineInfo &CI);
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MachineBasicBlock::iterator mergeSBufferLoadImmPair(CombineInfo &CI);
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MachineBasicBlock::iterator mergeBufferLoadPair(CombineInfo &CI);
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MachineBasicBlock::iterator mergeBufferStorePair(CombineInfo &CI);
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@@ -273,6 +279,11 @@ static unsigned getOpcodeWidth(const MachineInstr &MI, const SIInstrInfo &TII) {
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// FIXME: Handle d16 correctly
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return AMDGPU::getMUBUFElements(Opc);
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}
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if (TII.isMIMG(MI)) {
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uint64_t DMaskImm =
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TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm();
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return countPopulation(DMaskImm);
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}
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switch (Opc) {
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case AMDGPU::S_BUFFER_LOAD_DWORD_IMM:
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@@ -306,6 +317,15 @@ static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) {
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return BUFFER_STORE;
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}
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}
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if (TII.isMIMG(Opc)) {
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// Ignore instructions encoded without vaddr.
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if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) == -1)
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return UNKNOWN;
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// TODO: Support IMAGE_GET_RESINFO and IMAGE_GET_LOD.
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if (TII.get(Opc).mayStore() || !TII.get(Opc).mayLoad() || TII.isGather4(Opc))
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return UNKNOWN;
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return MIMG;
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}
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return UNKNOWN;
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case AMDGPU::S_BUFFER_LOAD_DWORD_IMM:
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case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM:
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@@ -331,6 +351,11 @@ static unsigned getInstSubclass(unsigned Opc, const SIInstrInfo &TII) {
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default:
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if (TII.isMUBUF(Opc))
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return AMDGPU::getMUBUFBaseOpcode(Opc);
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if (TII.isMIMG(Opc)) {
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const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);
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assert(Info);
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return Info->BaseOpcode;
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}
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return -1;
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case AMDGPU::DS_READ_B32:
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case AMDGPU::DS_READ_B32_gfx9:
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@@ -367,6 +392,14 @@ static unsigned getRegs(unsigned Opc, const SIInstrInfo &TII) {
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return result;
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}
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if (TII.isMIMG(Opc)) {
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unsigned result = VADDR | SRSRC;
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const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);
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if (Info && AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode)->Sampler)
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result |= SSAMP;
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return result;
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}
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switch (Opc) {
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default:
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return 0;
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@@ -416,14 +449,18 @@ void SILoadStoreOptimizer::CombineInfo::setMI(MachineBasicBlock::iterator MI,
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break;
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}
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int OffsetIdx =
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AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
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Offset0 = I->getOperand(OffsetIdx).getImm();
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if (InstClass == MIMG) {
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DMask0 = TII.getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm();
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} else {
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int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
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Offset0 = I->getOperand(OffsetIdx).getImm();
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}
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Width0 = getOpcodeWidth(*I, TII);
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if ((InstClass == DS_READ) || (InstClass == DS_WRITE)) {
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Offset0 &= 0xffff;
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} else {
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} else if (InstClass != MIMG) {
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GLC0 = TII.getNamedOperand(*I, AMDGPU::OpName::glc)->getImm();
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if (InstClass != S_BUFFER_LOAD_IMM) {
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SLC0 = TII.getNamedOperand(*I, AMDGPU::OpName::slc)->getImm();
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@@ -455,6 +492,10 @@ void SILoadStoreOptimizer::CombineInfo::setMI(MachineBasicBlock::iterator MI,
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AddrOpName[NumAddresses++] = AMDGPU::OpName::vaddr;
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}
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if (Regs & SSAMP) {
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AddrOpName[NumAddresses++] = AMDGPU::OpName::ssamp;
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}
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for (unsigned i = 0; i < NumAddresses; i++) {
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AddrIdx[i] = AMDGPU::getNamedOperandIdx(I->getOpcode(), AddrOpName[i]);
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AddrReg[i] = &I->getOperand(AddrIdx[i]);
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@@ -467,13 +508,19 @@ void SILoadStoreOptimizer::CombineInfo::setPaired(MachineBasicBlock::iterator MI
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const SIInstrInfo &TII) {
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Paired = MI;
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assert(InstClass == getInstClass(Paired->getOpcode(), TII));
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int OffsetIdx =
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AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::offset);
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Offset1 = Paired->getOperand(OffsetIdx).getImm();
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if (InstClass == MIMG) {
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DMask1 = TII.getNamedOperand(*Paired, AMDGPU::OpName::dmask)->getImm();
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} else {
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int OffsetIdx =
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AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::offset);
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Offset1 = Paired->getOperand(OffsetIdx).getImm();
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}
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Width1 = getOpcodeWidth(*Paired, TII);
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if ((InstClass == DS_READ) || (InstClass == DS_WRITE)) {
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Offset1 &= 0xffff;
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} else {
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} else if (InstClass != MIMG) {
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GLC1 = TII.getNamedOperand(*Paired, AMDGPU::OpName::glc)->getImm();
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if (InstClass != S_BUFFER_LOAD_IMM) {
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SLC1 = TII.getNamedOperand(*Paired, AMDGPU::OpName::slc)->getImm();
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@@ -588,7 +635,44 @@ static MachineMemOperand *combineKnownAdjacentMMOs(MachineFunction &MF,
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return MMO;
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}
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bool SILoadStoreOptimizer::dmasksCanBeCombined(const CombineInfo &CI, const SIInstrInfo &TII) {
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assert(CI.InstClass == MIMG);
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// Ignore instructions with tfe/lwe set.
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const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe);
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const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe);
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if ((TFEOp && TFEOp->getImm()) || (LWEOp && LWEOp->getImm()))
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return false;
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// Check other optional immediate operands for equality.
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unsigned OperandsToMatch[] = {AMDGPU::OpName::glc, AMDGPU::OpName::slc,
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AMDGPU::OpName::d16, AMDGPU::OpName::unorm,
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AMDGPU::OpName::da, AMDGPU::OpName::r128};
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for (auto op : OperandsToMatch) {
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int Idx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), op);
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if (AMDGPU::getNamedOperandIdx(CI.Paired->getOpcode(), op) != Idx)
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return false;
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if (Idx != -1 &&
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CI.I->getOperand(Idx).getImm() != CI.Paired->getOperand(Idx).getImm())
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return false;
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}
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// Check DMask for overlaps.
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unsigned MaxMask = std::max(CI.DMask0, CI.DMask1);
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unsigned MinMask = std::min(CI.DMask0, CI.DMask1);
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unsigned AllowedBitsForMin = llvm::countTrailingZeros(MaxMask);
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if ((1u << AllowedBitsForMin) <= MinMask)
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return false;
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return true;
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}
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bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI) {
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assert(CI.InstClass != MIMG);
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// XXX - Would the same offset be OK? Is there any reason this would happen or
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// be useful?
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if (CI.Offset0 == CI.Offset1)
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@@ -744,13 +828,18 @@ bool SILoadStoreOptimizer::findMatchingInst(CombineInfo &CI) {
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if (Match) {
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CI.setPaired(MBBI, *TII);
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// Check both offsets fit in the reduced range.
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// Check both offsets (or masks for MIMG) can be combined and fit in the
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// reduced range.
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bool canBeCombined =
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CI.InstClass == MIMG
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? dmasksCanBeCombined(CI, *TII)
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: widthsFit(*STM, CI) && offsetsCanBeCombined(CI);
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// We also need to go through the list of instructions that we plan to
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// move and make sure they are all safe to move down past the merged
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// instruction.
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if (widthsFit(*STM, CI) && offsetsCanBeCombined(CI))
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if (canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, AA))
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return true;
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if (canBeCombined && canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, AA))
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return true;
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}
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// We've found a load/store that we couldn't merge for some reason.
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@@ -945,6 +1034,60 @@ SILoadStoreOptimizer::mergeWrite2Pair(CombineInfo &CI) {
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return Write2;
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}
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MachineBasicBlock::iterator
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SILoadStoreOptimizer::mergeImagePair(CombineInfo &CI) {
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MachineBasicBlock *MBB = CI.I->getParent();
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DebugLoc DL = CI.I->getDebugLoc();
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const unsigned Opcode = getNewOpcode(CI);
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const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI);
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Register DestReg = MRI->createVirtualRegister(SuperRC);
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unsigned MergedDMask = CI.DMask0 | CI.DMask1;
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unsigned DMaskIdx =
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AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask);
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auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg);
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for (unsigned I = 1, E = (*CI.I).getNumOperands(); I != E; ++I) {
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if (I == DMaskIdx)
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MIB.addImm(MergedDMask);
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else
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MIB.add((*CI.I).getOperand(I));
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}
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// It shouldn't be possible to get this far if the two instructions
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// don't have a single memoperand, because MachineInstr::mayAlias()
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// will return true if this is the case.
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assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand());
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const MachineMemOperand *MMOa = *CI.I->memoperands_begin();
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const MachineMemOperand *MMOb = *CI.Paired->memoperands_begin();
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MachineInstr *New = MIB.addMemOperand(combineKnownAdjacentMMOs(*MBB->getParent(), MMOa, MMOb));
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std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI);
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const unsigned SubRegIdx0 = std::get<0>(SubRegIdx);
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const unsigned SubRegIdx1 = std::get<1>(SubRegIdx);
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// Copy to the old destination registers.
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const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
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const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata);
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const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata);
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BuildMI(*MBB, CI.Paired, DL, CopyDesc)
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.add(*Dest0) // Copy to same destination including flags and sub reg.
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.addReg(DestReg, 0, SubRegIdx0);
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MachineInstr *Copy1 = BuildMI(*MBB, CI.Paired, DL, CopyDesc)
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.add(*Dest1)
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.addReg(DestReg, RegState::Kill, SubRegIdx1);
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moveInstsAfter(Copy1, CI.InstsToMove);
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CI.I->eraseFromParent();
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CI.Paired->eraseFromParent();
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return New;
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}
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MachineBasicBlock::iterator
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SILoadStoreOptimizer::mergeSBufferLoadImmPair(CombineInfo &CI) {
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MachineBasicBlock *MBB = CI.I->getParent();
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@@ -1077,6 +1220,9 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const CombineInfo &CI) {
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case 4:
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return AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM;
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}
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case MIMG:
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assert("No overlaps" && (countPopulation(CI.DMask0 | CI.DMask1) == Width));
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return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width);
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}
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}
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@@ -1086,7 +1232,13 @@ SILoadStoreOptimizer::getSubRegIdxs(const CombineInfo &CI) {
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if (CI.Width0 == 0 || CI.Width0 == 0 || CI.Width0 + CI.Width1 > 4)
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return std::make_pair(0, 0);
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bool ReverseOrder = CI.Offset0 > CI.Offset1;
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bool ReverseOrder;
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if (CI.InstClass == MIMG) {
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assert((countPopulation(CI.DMask0 | CI.DMask1) == CI.Width0 + CI.Width1) &&
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"No overlaps");
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ReverseOrder = CI.DMask0 > CI.DMask1;
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} else
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ReverseOrder = CI.Offset0 > CI.Offset1;
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static const unsigned Idxs[4][4] = {
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{AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3},
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@@ -1655,6 +1807,15 @@ SILoadStoreOptimizer::optimizeInstsWithSameBaseAddr(
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OptimizeListAgain |= (CI.Width0 + CI.Width1) < 4;
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}
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break;
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case MIMG:
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if (findMatchingInst(CI)) {
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Modified = true;
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removeCombinedInst(MergeList, *CI.Paired);
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MachineBasicBlock::iterator NewMI = mergeImagePair(CI);
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CI.setMI(NewMI, *TII, *STM);
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OptimizeListAgain |= (CI.Width0 + CI.Width1) < 4;
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}
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break;
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}
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// Clear the InstsToMove after we have finished searching so we don't have
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// stale values left over if we search for this CI again in another pass
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@@ -0,0 +1,471 @@
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# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX9 %s
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# GFX9-LABEL: name: image_load_merged_v1v3
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# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
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# GFX9: %{{[0-9]+}}:vgpr_32 = COPY %8.sub0
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# GFX9: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub1_sub2_sub3
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name: image_load_merged_v1v3
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body: |
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bb.0.entry:
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
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%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
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%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
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%4:vgpr_32 = COPY %2.sub3
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%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
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%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5:vreg_128, %3:sreg_256, 1, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
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%7:vreg_96 = IMAGE_LOAD_V3_V4 %5:vreg_128, %3:sreg_256, 14, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
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...
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---
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# GFX9-LABEL: name: image_load_merged_v1v3_reversed
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# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
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# GFX9: %{{[0-9]+}}:vgpr_32 = COPY %8.sub3
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# GFX9: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub0_sub1_sub2
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name: image_load_merged_v1v3_reversed
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body: |
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bb.0.entry:
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
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%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
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%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
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%4:vgpr_32 = COPY %2.sub3
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%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
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%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5:vreg_128, %3:sreg_256, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
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%7:vreg_96 = IMAGE_LOAD_V3_V4 %5:vreg_128, %3:sreg_256, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
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...
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---
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|
||||
# GFX9-LABEL: name: image_load_merged_v2v2
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec, implicit $exec :: (dereferenceable load 16, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_64 = COPY %8.sub0_sub1
|
||||
# GFX9: %{{[0-9]+}}:vreg_64 = COPY killed %8.sub2_sub3
|
||||
|
||||
name: image_load_merged_v2v2
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vreg_64 = IMAGE_LOAD_V2_V4 %5:vreg_128, %3:sreg_256, 3, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 8, align 16, addrspace 4)
|
||||
%7:vreg_64 = IMAGE_LOAD_V2_V4 %5:vreg_128, %3:sreg_256, 12, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 8, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_merged_v2v2_reversed
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec, implicit $exec :: (dereferenceable load 16, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_64 = COPY %8.sub2_sub3
|
||||
# GFX9: %{{[0-9]+}}:vreg_64 = COPY killed %8.sub0_sub1
|
||||
|
||||
name: image_load_merged_v2v2_reversed
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vreg_64 = IMAGE_LOAD_V2_V4 %5:vreg_128, %3:sreg_256, 12, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 8, align 16, addrspace 4)
|
||||
%7:vreg_64 = IMAGE_LOAD_V2_V4 %5:vreg_128, %3:sreg_256, 3, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 8, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_merged_v3v1
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec, implicit $exec :: (dereferenceable load 16, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = COPY %8.sub0_sub1_sub2
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %8.sub3
|
||||
|
||||
name: image_load_merged_v3v1
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vreg_96 = IMAGE_LOAD_V3_V4 %5:vreg_128, %3:sreg_256, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
%7:vgpr_32 = IMAGE_LOAD_V1_V4 %5:vreg_128, %3:sreg_256, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_merged_v3v1_reversed
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec, implicit $exec :: (dereferenceable load 16, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = COPY %8.sub1_sub2_sub3
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %8.sub0
|
||||
|
||||
name: image_load_merged_v3v1_reversed
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vreg_96 = IMAGE_LOAD_V3_V4 %5:vreg_128, %3:sreg_256, 14, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
%7:vgpr_32 = IMAGE_LOAD_V1_V4 %5:vreg_128, %3:sreg_256, 1, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_divided_merged
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
|
||||
|
||||
name: image_load_divided_merged
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5:vreg_128, %3:sreg_256, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%8:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%9:vreg_96 = IMAGE_LOAD_V3_V4 %7:vreg_128, %3:sreg_256, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
%10:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%11:vreg_96 = IMAGE_LOAD_V3_V4 %5:vreg_128, %3:sreg_256, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_divided_not_merged
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_divided_not_merged
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vreg_128 = COPY %2
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5:vreg_128, %3:sreg_256, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
IMAGE_STORE_V4_V4 %4:vreg_128, %5:vreg_128, %3:sreg_256, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5:vreg_128, %3:sreg_256, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_dmask_overlapped_not_merged
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 4, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_dmask_overlapped_not_merged
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5:vreg_128, %3:sreg_256, 4, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5:vreg_128, %3:sreg_256, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_dmask_not_disjoint_not_merged
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 4, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 11, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_dmask_not_disjoint_not_merged
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5:vreg_128, %3:sreg_256, 4, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5:vreg_128, %3:sreg_256, 11, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_0
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %6, %3, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_0
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%7:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%8:vreg_96 = IMAGE_LOAD_V3_V4 %6, %3, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_1
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %6, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %6, %4, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_1
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%5:vgpr_32 = COPY %2.sub3
|
||||
%6:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%7:vgpr_32 = IMAGE_LOAD_V1_V4 %6, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%8:vreg_96 = IMAGE_LOAD_V3_V4 %6, %4, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_10
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, -1, 1, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_10
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, -1, 1, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_3
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 1, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_3
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 1, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_4
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 1, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_4
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 1, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_5
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 1, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_5
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 1, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_6
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 1, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_6
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 1, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_7
|
||||
# GFX9: %{{[0-9]+}}:vreg_64 = IMAGE_LOAD_V2_V4 %5, %3, 8, 0, 0, 0, 0, 1, 0, -1, 0, implicit $exec :: (dereferenceable load 8, align 16, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_7
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vreg_64 = IMAGE_LOAD_V2_V4 %5, %3, 8, 0, 0, 0, 0, 1, 0, -1, 0, implicit $exec :: (dereferenceable load 8, align 16, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_8
|
||||
# GFX9: %{{[0-9]+}}:vreg_64 = IMAGE_LOAD_V2_V4 %5, %3, 8, 0, 0, 0, 0, 0, 1, -1, 0, implicit $exec :: (dereferenceable load 8, align 16, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_8
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vreg_64 = IMAGE_LOAD_V2_V4 %5, %3, 8, 0, 0, 0, 0, 0, 1, -1, 0, implicit $exec :: (dereferenceable load 8, align 16, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_not_merged_9
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
|
||||
name: image_load_not_merged_9
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_V1_V4 %5, %3, 8, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_V3_V4 %5, %3, 7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_mip_merged_v1v3
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_MIP_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = COPY %8.sub0
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub1_sub2_sub3
|
||||
|
||||
name: image_load_mip_merged_v1v3
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_MIP_V1_V4 %5:vreg_128, %3:sreg_256, 1, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_MIP_V3_V4 %5:vreg_128, %3:sreg_256, 14, 0, 0, 0, 0, 0, 0, -1, 0, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
|
||||
|
||||
# GFX9-LABEL: name: image_load_mip_pck_merged_v1v3
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_MIP_PCK_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, implicit $exec, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = COPY %8.sub0
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub1_sub2_sub3
|
||||
|
||||
name: image_load_mip_pck_merged_v1v3
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_MIP_PCK_V1_V4 %5:vreg_128, %3:sreg_256, 1, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_MIP_PCK_V3_V4 %5:vreg_128, %3:sreg_256, 14, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
|
||||
|
||||
# GFX9-LABEL: name: image_load_mip_pck_sgn_merged_v1v3
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_MIP_PCK_SGN_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, implicit $exec, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = COPY %8.sub0
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub1_sub2_sub3
|
||||
|
||||
name: image_load_mip_pck_sgn_merged_v1v3
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_MIP_PCK_SGN_V1_V4 %5:vreg_128, %3:sreg_256, 1, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_MIP_PCK_SGN_V3_V4 %5:vreg_128, %3:sreg_256, 14, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_pck_merged_v1v3
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_PCK_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, implicit $exec, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = COPY %8.sub0
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub1_sub2_sub3
|
||||
|
||||
name: image_load_pck_merged_v1v3
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_PCK_V1_V4 %5:vreg_128, %3:sreg_256, 1, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_PCK_V3_V4 %5:vreg_128, %3:sreg_256, 14, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
|
||||
# GFX9-LABEL: name: image_load_pck_sgn_merged_v1v3
|
||||
# GFX9: %{{[0-9]+}}:vreg_128 = IMAGE_LOAD_PCK_SGN_V4_V4 %5, %3, 15, 0, 0, 0, 0, 0, 0, -1, implicit $exec, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
|
||||
# GFX9: %{{[0-9]+}}:vgpr_32 = COPY %8.sub0
|
||||
# GFX9: %{{[0-9]+}}:vreg_96 = COPY killed %8.sub1_sub2_sub3
|
||||
|
||||
name: image_load_pck_sgn_merged_v1v3
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%2:sgpr_128 =COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sreg_256 = S_LOAD_DWORDX8_IMM %1, 208, 0, 0
|
||||
%4:vgpr_32 = COPY %2.sub3
|
||||
%5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16)
|
||||
%6:vgpr_32 = IMAGE_LOAD_PCK_SGN_V1_V4 %5:vreg_128, %3:sreg_256, 1, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load 4, addrspace 4)
|
||||
%7:vreg_96 = IMAGE_LOAD_PCK_SGN_V3_V4 %5:vreg_128, %3:sreg_256, 14, 0, 0, 0, 0, 0, 0, -1, implicit $exec :: (dereferenceable load 12, align 16, addrspace 4)
|
||||
...
|
||||
---
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user