RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-11-26 05:00:39 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Starting to refactor Target to separate out code that's needed to fully describe

Browse Source 
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-06-24 01:44:41 +00:00
parent 66dddd1da3
commit a347f85dbe
52 changed files with 502 additions and 271 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Makefile.rules
View File

@ -1725,15 +1725,20 @@ $(ObjDir)/%GenRegisterNames.inc.tmp : %.td $(ObjDir)/.dir
$(Echo) "Building $(<F) register names with tblgen"
$(Verb) $(TableGen) -gen-register-enums -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenRegisterDesc.inc.tmp): \
$(ObjDir)/%GenRegisterDesc.inc.tmp : %.td $(ObjDir)/.dir
$(Echo) "Building $(<F) register descriptions with tblgen"
$(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenRegisterInfo.h.inc.tmp): \
$(ObjDir)/%GenRegisterInfo.h.inc.tmp : %.td $(ObjDir)/.dir
$(Echo) "Building $(<F) register information header with tblgen"
$(Verb) $(TableGen) -gen-register-desc-header -o $(call SYSPATH, $@) $<
$(Verb) $(TableGen) -gen-register-info-header -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \
$(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir
$(Echo) "Building $(<F) register info implementation with tblgen"
$(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
$(Verb) $(TableGen) -gen-register-info -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenInstrNames.inc.tmp): \
$(ObjDir)/%GenInstrNames.inc.tmp : %.td $(ObjDir)/.dir

123
include/llvm/MC/MCRegisterInfo.h Normal file
View File

@ -0,0 +1,123 @@
//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes an abstract interface used to get information about a
// target machines register file. This information is used for a variety of
// purposed, especially register allocation.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_MC_MCREGISTERINFO_H
#define LLVM_MC_MCREGISTERINFO_H
#include <cassert>
namespace llvm {
/// TargetRegisterDesc - This record contains all of the information known about
/// a particular register. The Overlaps field contains a pointer to a zero
/// terminated array of registers that this register aliases, starting with
/// itself. This is needed for architectures like X86 which have AL alias AX
/// alias EAX. The SubRegs field is a zero terminated array of registers that
/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
/// AX. The SuperRegs field is a zero terminated array of registers that are
/// super-registers of the specific register, e.g. RAX, EAX, are super-registers
/// of AX.
///
struct TargetRegisterDesc {
const char *Name; // Printable name for the reg (for debugging)
const unsigned *Overlaps; // Overlapping registers, described above
const unsigned *SubRegs; // Sub-register set, described above
const unsigned *SuperRegs; // Super-register set, described above
};
/// MCRegisterInfo base class - We assume that the target defines a static
/// array of TargetRegisterDesc objects that represent all of the machine
/// registers that the target has. As such, we simply have to track a pointer
/// to this array so that we can turn register number into a register
/// descriptor.
///
class MCRegisterInfo {
private:
const TargetRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the array
public:
/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
/// auto-generated routines. *DO NOT USE*.
void InitMCRegisterInfo(const TargetRegisterDesc *D, unsigned NR) {
Desc = D;
NumRegs = NR;
}
const TargetRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
"Attempting to access record for invalid register number!");
return Desc[RegNo];
}
/// Provide a get method, equivalent to [], but more useful if we have a
/// pointer to this object.
///
const TargetRegisterDesc &get(unsigned RegNo) const {
return operator[](RegNo);
}
/// getAliasSet - Return the set of registers aliased by the specified
/// register, or a null list of there are none. The list returned is zero
/// terminated.
///
const unsigned *getAliasSet(unsigned RegNo) const {
// The Overlaps set always begins with Reg itself.
return get(RegNo).Overlaps + 1;
}
/// getOverlaps - Return a list of registers that overlap Reg, including
/// itself. This is the same as the alias set except Reg is included in the
/// list.
/// These are exactly the registers in { x | regsOverlap(x, Reg) }.
///
const unsigned *getOverlaps(unsigned RegNo) const {
return get(RegNo).Overlaps;
}
/// getSubRegisters - Return the list of registers that are sub-registers of
/// the specified register, or a null list of there are none. The list
/// returned is zero terminated and sorted according to super-sub register
/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
///
const unsigned *getSubRegisters(unsigned RegNo) const {
return get(RegNo).SubRegs;
}
/// getSuperRegisters - Return the list of registers that are super-registers
/// of the specified register, or a null list of there are none. The list
/// returned is zero terminated and sorted according to super-sub register
/// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
///
const unsigned *getSuperRegisters(unsigned RegNo) const {
return get(RegNo).SuperRegs;
}
/// getName - Return the human-readable symbolic target-specific name for the
/// specified physical register.
const char *getName(unsigned RegNo) const {
return get(RegNo).Name;
}
/// getNumRegs - Return the number of registers this target has (useful for
/// sizing arrays holding per register information)
unsigned getNumRegs() const {
return NumRegs;
}
};
} // End llvm namespace
#endif

100
include/llvm/Target/TargetRegisterInfo.h
View File

@ -16,6 +16,7 @@
#ifndef LLVM_TARGET_TARGETREGISTERINFO_H
#define LLVM_TARGET_TARGETREGISTERINFO_H
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/ADT/ArrayRef.h"
@ -32,25 +33,6 @@ class RegScavenger;
template<class T> class SmallVectorImpl;
class raw_ostream;
/// TargetRegisterDesc - This record contains all of the information known about
/// a particular register. The Overlaps field contains a pointer to a zero
/// terminated array of registers that this register aliases, starting with
/// itself. This is needed for architectures like X86 which have AL alias AX
/// alias EAX. The SubRegs field is a zero terminated array of registers that
/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
/// AX. The SuperRegs field is a zero terminated array of registers that are
/// super-registers of the specific register, e.g. RAX, EAX, are super-registers
/// of AX.
///
struct TargetRegisterDesc {
const char *Name; // Printable name for the reg (for debugging)
const unsigned *Overlaps; // Overlapping registers, described above
const unsigned *SubRegs; // Sub-register set, described above
const unsigned *SuperRegs; // Super-register set, described above
unsigned CostPerUse; // Extra cost of instructions using register.
bool inAllocatableClass; // Register belongs to an allocatable regclass.
};
class TargetRegisterClass {
public:
typedef const unsigned* iterator;
@ -274,6 +256,12 @@ public:
bool isAllocatable() const { return Allocatable; }
};
/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
/// registers. These are used by codegen, not by MC.
struct TargetRegisterInfoDesc {
unsigned CostPerUse; // Extra cost of instructions using register.
bool inAllocatableClass; // Register belongs to an allocatable regclass.
};
/// TargetRegisterInfo base class - We assume that the target defines a static
/// array of TargetRegisterDesc objects that represent all of the machine
@ -281,20 +269,17 @@ public:
/// to this array so that we can turn register number into a register
/// descriptor.
///
class TargetRegisterInfo {
class TargetRegisterInfo : public MCRegisterInfo {
public:
typedef const TargetRegisterClass * const * regclass_iterator;
private:
const TargetRegisterDesc *Desc; // Pointer to the descriptor array
const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
const char *const *SubRegIndexNames; // Names of subreg indexes.
unsigned NumRegs; // Number of entries in the array
regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
int CallFrameSetupOpcode, CallFrameDestroyOpcode;
protected:
TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
regclass_iterator RegClassBegin,
regclass_iterator RegClassEnd,
const char *const *subregindexnames,
@ -379,71 +364,16 @@ public:
BitVector getAllocatableSet(const MachineFunction &MF,
const TargetRegisterClass *RC = NULL) const;
const TargetRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
"Attempting to access record for invalid register number!");
return Desc[RegNo];
}
/// Provide a get method, equivalent to [], but more useful if we have a
/// pointer to this object.
///
const TargetRegisterDesc &get(unsigned RegNo) const {
return operator[](RegNo);
}
/// getAliasSet - Return the set of registers aliased by the specified
/// register, or a null list of there are none. The list returned is zero
/// terminated.
///
const unsigned *getAliasSet(unsigned RegNo) const {
// The Overlaps set always begins with Reg itself.
return get(RegNo).Overlaps + 1;
}
/// getOverlaps - Return a list of registers that overlap Reg, including
/// itself. This is the same as the alias set except Reg is included in the
/// list.
/// These are exactly the registers in { x | regsOverlap(x, Reg) }.
///
const unsigned *getOverlaps(unsigned RegNo) const {
return get(RegNo).Overlaps;
}
/// getSubRegisters - Return the list of registers that are sub-registers of
/// the specified register, or a null list of there are none. The list
/// returned is zero terminated and sorted according to super-sub register
/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
///
const unsigned *getSubRegisters(unsigned RegNo) const {
return get(RegNo).SubRegs;
}
/// getSuperRegisters - Return the list of registers that are super-registers
/// of the specified register, or a null list of there are none. The list
/// returned is zero terminated and sorted according to super-sub register
/// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
///
const unsigned *getSuperRegisters(unsigned RegNo) const {
return get(RegNo).SuperRegs;
}
/// getName - Return the human-readable symbolic target-specific name for the
/// specified physical register.
const char *getName(unsigned RegNo) const {
return get(RegNo).Name;
}
/// getCostPerUse - Return the additional cost of using this register instead
/// of other registers in its class.
unsigned getCostPerUse(unsigned RegNo) const {
return get(RegNo).CostPerUse;
return InfoDesc[RegNo].CostPerUse;
}
/// getNumRegs - Return the number of registers this target has (useful for
/// sizing arrays holding per register information)
unsigned getNumRegs() const {
return NumRegs;
/// isInAllocatableClass - Return true if the register is in the allocation
/// of any register class.
bool isInAllocatableClass(unsigned RegNo) const {
return InfoDesc[RegNo].inAllocatableClass;
}
/// getSubRegIndexName - Return the human-readable symbolic target-specific

39
include/llvm/Target/TargetRegistry.h
View File

@ -33,6 +33,7 @@ namespace llvm {
class MCContext;
class MCDisassembler;
class MCInstPrinter;
class MCRegisterInfo;
class MCStreamer;
class TargetAsmBackend;
class TargetAsmLexer;
@ -64,7 +65,9 @@ namespace llvm {
typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);
typedef MCAsmInfo *(*AsmInfoCtorFnTy)(const Target &T,
StringRef TT);
StringRef TT);
typedef MCRegisterInfo *(*RegInfoCtorFnTy)(const Target &T,
StringRef TT);
typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
const std::string &TT,
const std::string &Features);
@ -120,8 +123,14 @@ namespace llvm {
/// HasJIT - Whether this target supports the JIT.
bool HasJIT;
/// AsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if
/// registered.
AsmInfoCtorFnTy AsmInfoCtorFn;
/// RegInfoCtorFn - Constructor function for this target's MCRegisterInfo,
/// if registered.
RegInfoCtorFnTy RegInfoCtorFn;
/// TargetMachineCtorFn - Construction function for this target's
/// TargetMachine, if registered.
TargetMachineCtorTy TargetMachineCtorFn;
@ -231,6 +240,19 @@ namespace llvm {
return AsmInfoCtorFn(*this, Triple);
}
/// createRegInfo - Create a MCRegisterInfo implementation for the specified
/// target triple.
///
/// \arg Triple - This argument is used to determine the target machine
/// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
MCRegisterInfo *createRegInfo(StringRef Triple) const {
if (!RegInfoCtorFn)
return 0;
return RegInfoCtorFn(*this, Triple);
}
/// createTargetMachine - Create a target specific machine implementation
/// for the specified \arg Triple.
///
@ -444,6 +466,21 @@ namespace llvm {
T.AsmInfoCtorFn = Fn;
}
/// RegisterRegInfo - Register a MCRegisterInfo implementation for the
/// given target.
///
/// Clients are responsible for ensuring that registration doesn't occur
/// while another thread is attempting to access the registry. Typically
/// this is done by initializing all targets at program startup.
///
/// @param T - The target being registered.
/// @param Fn - A function to construct a MCRegisterInfo for the target.
static void RegisterRegInfo(Target &T, Target::RegInfoCtorFnTy Fn) {
// Ignore duplicate registration.
if (!T.RegInfoCtorFn)
T.RegInfoCtorFn = Fn;
}
/// RegisterTargetMachine - Register a TargetMachine implementation for the
/// given target.
///

2
lib/CodeGen/RegisterClassInfo.h
View File

@ -112,7 +112,7 @@ public:
/// register, so a register allocator needs to track its liveness and
/// availability.
bool isAllocatable(unsigned PhysReg) const {
return TRI->get(PhysReg).inAllocatableClass && !isReserved(PhysReg);
return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
}
};
} // end namespace llvm

7
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -39,6 +39,8 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/CommandLine.h"
#include "ARMGenRegisterDesc.inc"
#include "ARMGenRegisterInfo.inc"
using namespace llvm;
@ -54,7 +56,8 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
const ARMSubtarget &sti)
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
: ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc,
ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti),
FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
BasePtr(ARM::R6) {
@ -1287,5 +1290,3 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.setDesc(TII.get(ARM::t2SUBri));
}
}
#include "ARMGenRegisterInfo.inc"

5
lib/Target/ARM/CMakeLists.txt
View File

@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS ARM.td)
tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(ARMGenRegisterNames.inc -gen-register-enums)
tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
tablegen(ARMGenRegisterDesc.inc -gen-register-desc)
tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(ARMGenRegisterInfo.inc -gen-register-info)
tablegen(ARMGenInstrNames.inc -gen-instr-enums)
tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
tablegen(ARMGenCodeEmitter.inc -gen-emitter)

7
lib/Target/ARM/Makefile
View File

@ -12,9 +12,10 @@ LIBRARYNAME = LLVMARMCodeGen
TARGET = ARM
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
ARMGenInstrInfo.inc ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \
ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
ARMGenInstrNames.inc ARMGenInstrInfo.inc \
ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
ARMGenDAGISel.inc ARMGenSubtarget.inc \
ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
ARMGenDecoderTables.inc ARMGenEDInfo.inc \

9
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -33,10 +33,13 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
#include "AlphaGenRegisterDesc.inc"
#include "AlphaGenRegisterInfo.inc"
using namespace llvm;
AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
: AlphaGenRegisterInfo(AlphaRegDesc, AlphaRegInfoDesc,
Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
TII(tii) {
}
@ -204,10 +207,8 @@ int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
return -1;
}
#include "AlphaGenRegisterInfo.inc"
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
{
std::string s(RegisterDescriptors[reg].Name);
std::string s(AlphaRegDesc[reg].Name);
return s;
}

5
lib/Target/Alpha/CMakeLists.txt
View File

@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS Alpha.td)
tablegen(AlphaGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
tablegen(AlphaGenRegisterInfo.inc -gen-register-desc)
tablegen(AlphaGenRegisterDesc.inc -gen-register-desc)
tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)

6
lib/Target/Alpha/Makefile
View File

@ -12,9 +12,9 @@ LIBRARYNAME = LLVMAlphaCodeGen
TARGET = Alpha
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \
AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \
AlphaGenInstrInfo.inc \
BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \
AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \
AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
AlphaGenCallingConv.inc AlphaGenSubtarget.inc

8
lib/Target/Blackfin/BlackfinRegisterInfo.cpp
View File

@ -29,11 +29,14 @@
#include "llvm/Type.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "BlackfinGenRegisterDesc.inc"
#include "BlackfinGenRegisterInfo.inc"
using namespace llvm;
BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
const TargetInstrInfo &tii)
: BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
: BlackfinGenRegisterInfo(BlackfinRegDesc, BlackfinRegInfoDesc,
BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
Subtarget(st),
TII(tii) {}
@ -356,6 +359,3 @@ int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum,
llvm_unreachable("What is the dwarf register number");
return -1;
}
#include "BlackfinGenRegisterInfo.inc"

5
lib/Target/Blackfin/CMakeLists.txt
View File

@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS Blackfin.td)
tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(BlackfinGenRegisterNames.inc -gen-register-enums)
tablegen(BlackfinGenRegisterInfo.inc -gen-register-desc)
tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc)
tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)

5
lib/Target/Blackfin/Makefile
View File

@ -12,8 +12,9 @@ LIBRARYNAME = LLVMBlackfinCodeGen
TARGET = Blackfin
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterNames.inc \
BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \
BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
BlackfinGenInstrNames.inc \
BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc

3
lib/Target/CellSPU/Makefile
View File

@ -10,8 +10,9 @@
LEVEL = ../../..
LIBRARYNAME = LLVMCellSPUCodeGen
TARGET = SPU
BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterNames.inc \
BUILT_SOURCES = SPUGenInstrNames.inc \
SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \
SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \
SPUGenInstrInfo.inc SPUGenDAGISel.inc \
SPUGenSubtarget.inc SPUGenCallingConv.inc

7
lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -42,6 +42,8 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
#include "SPUGenRegisterDesc.inc"
#include "SPUGenRegisterInfo.inc"
using namespace llvm;
@ -185,7 +187,8 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
const TargetInstrInfo &tii) :
SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
SPUGenRegisterInfo(SPURegDesc, SPURegInfoDesc,
SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
Subtarget(subtarget),
TII(tii)
{
@ -371,5 +374,3 @@ SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
assert( Reg && "Register scavenger failed");
return Reg;
}
#include "SPUGenRegisterInfo.inc"

5
lib/Target/MBlaze/CMakeLists.txt
View File

@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS MBlaze.td)
tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(MBlazeGenRegisterNames.inc -gen-register-enums)
tablegen(MBlazeGenRegisterInfo.inc -gen-register-desc)
tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc)
tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)

9
lib/Target/MBlaze/MBlazeRegisterInfo.cpp
View File

@ -36,12 +36,14 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "MBlazeGenRegisterDesc.inc"
#include "MBlazeGenRegisterInfo.inc"
using namespace llvm;
MBlazeRegisterInfo::
MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
: MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
: MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc,
MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
Subtarget(ST), TII(tii) {}
/// getRegisterNumbering - Given the enum value for some register, e.g.
@ -359,6 +361,3 @@ int MBlazeRegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
#include "MBlazeGenRegisterInfo.inc"

13
lib/Target/MBlaze/Makefile
View File

@ -12,12 +12,13 @@ TARGET = MBlaze
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \
MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
MBlazeGenEDInfo.inc
MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \
MBlazeGenInstrNames.inc \
MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
MBlazeGenEDInfo.inc
DIRS = InstPrinter AsmParser Disassembler TargetInfo

5
lib/Target/MSP430/CMakeLists.txt
View File

@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS MSP430.td)
tablegen(MSP430GenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(MSP430GenRegisterNames.inc -gen-register-enums)
tablegen(MSP430GenRegisterInfo.inc -gen-register-desc)
tablegen(MSP430GenRegisterDesc.inc -gen-register-desc)
tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header)
tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)

7
lib/Target/MSP430/MSP430RegisterInfo.cpp
View File

@ -25,13 +25,16 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/Support/ErrorHandling.h"
#include "MSP430GenRegisterDesc.inc"
#include "MSP430GenRegisterInfo.inc"
using namespace llvm;
// FIXME: Provide proper call frame setup / destroy opcodes.
MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
const TargetInstrInfo &tii)
: MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
: MSP430GenRegisterInfo(MSP430RegDesc, MSP430RegInfoDesc,
MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
TM(tm), TII(tii) {
StackAlign = TM.getFrameLowering()->getStackAlignment();
}
@ -250,5 +253,3 @@ int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
llvm_unreachable("Not implemented yet!");
return 0;
}
#include "MSP430GenRegisterInfo.inc"

3
lib/Target/MSP430/Makefile
View File

@ -13,7 +13,8 @@ TARGET = MSP430
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \
MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \
MSP430GenInstrNames.inc \
MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
MSP430GenSubtarget.inc

5
lib/Target/Mips/CMakeLists.txt
View File

@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS Mips.td)
tablegen(MipsGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(MipsGenRegisterNames.inc -gen-register-enums)
tablegen(MipsGenRegisterInfo.inc -gen-register-desc)
tablegen(MipsGenRegisterDesc.inc -gen-register-desc)
tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(MipsGenRegisterInfo.inc -gen-register-info)
tablegen(MipsGenInstrNames.inc -gen-instr-enums)
tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
tablegen(MipsGenAsmWriter.inc -gen-asm-writer)

3
lib/Target/Mips/Makefile
View File

@ -13,7 +13,8 @@ TARGET = Mips
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
MipsGenInstrNames.inc \
MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
MipsGenSubtarget.inc

7
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -35,12 +35,15 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "MipsGenRegisterDesc.inc"
#include "MipsGenRegisterInfo.inc"
using namespace llvm;
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
const TargetInstrInfo &tii)
: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
: MipsGenRegisterInfo(MipsRegDesc, MipsRegInfoDesc,
Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
Subtarget(ST), TII(tii) {}
/// getRegisterNumbering - Given the enum value for some register, e.g.
@ -285,5 +288,3 @@ getDwarfRegNum(unsigned RegNum, bool isEH) const {
int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
#include "MipsGenRegisterInfo.inc"

5
lib/Target/PTX/CMakeLists.txt
View File

@ -5,8 +5,9 @@ tablegen(PTXGenCallingConv.inc -gen-callingconv)
tablegen(PTXGenDAGISel.inc -gen-dag-isel)
tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
tablegen(PTXGenInstrNames.inc -gen-instr-enums)
tablegen(PTXGenRegisterInfo.inc -gen-register-desc)
tablegen(PTXGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(PTXGenRegisterDesc.inc -gen-register-desc)
tablegen(PTXGenRegisterInfo.inc -gen-register-info)
tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(PTXGenRegisterNames.inc -gen-register-enums)
tablegen(PTXGenSubtarget.inc -gen-subtarget)

1
lib/Target/PTX/Makefile
View File

@ -17,6 +17,7 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \
PTXGenDAGISel.inc \
PTXGenInstrInfo.inc \
PTXGenInstrNames.inc \
PTXGenRegisterDesc.inc \
PTXGenRegisterInfo.inc \
PTXGenRegisterInfo.h.inc \
PTXGenRegisterNames.inc \

6
lib/Target/PTX/PTXRegisterInfo.cpp
View File

@ -19,9 +19,15 @@
using namespace llvm;
#include "PTXGenRegisterDesc.inc"
#include "PTXGenRegisterInfo.inc"
PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
const TargetInstrInfo &TII)
: PTXGenRegisterInfo(PTXRegDesc, PTXRegInfoDesc) {
}
void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj,
RegScavenger *RS) const {

2
lib/Target/PTX/PTXRegisterInfo.h
View File

@ -25,7 +25,7 @@ class MachineFunction;
struct PTXRegisterInfo : public PTXGenRegisterInfo {
PTXRegisterInfo(PTXTargetMachine &TM,
const TargetInstrInfo &TII) {}
const TargetInstrInfo &TII);
virtual const unsigned
*getCalleeSavedRegs(const MachineFunction *MF = 0) const {

5
lib/Target/PowerPC/CMakeLists.txt
View File

@ -5,8 +5,9 @@ tablegen(PPCGenRegisterNames.inc -gen-register-enums)
tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
tablegen(PPCGenCodeEmitter.inc -gen-emitter)
tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(PPCGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(PPCGenRegisterInfo.inc -gen-register-desc)
tablegen(PPCGenRegisterDesc.inc -gen-register-desc)
tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(PPCGenRegisterInfo.inc -gen-register-info)
tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
tablegen(PPCGenDAGISel.inc -gen-dag-isel)
tablegen(PPCGenCallingConv.inc -gen-callingconv)

1
lib/Target/PowerPC/Makefile
View File

@ -14,6 +14,7 @@ TARGET = PPC
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
PPCGenRegisterDesc.inc \
PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
PPCGenInstrInfo.inc PPCGenDAGISel.inc \
PPCGenSubtarget.inc PPCGenCallingConv.inc \

7
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -43,6 +43,8 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
#include "PPCGenRegisterDesc.inc"
#include "PPCGenRegisterInfo.inc"
// FIXME (64-bit): Eventually enable by default.
namespace llvm {
@ -110,7 +112,8 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
const TargetInstrInfo &tii)
: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
: PPCGenRegisterInfo(PPCRegDesc, PPCRegInfoDesc,
PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
Subtarget(ST), TII(tii) {
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
@ -710,5 +713,3 @@ int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour);
}
#include "PPCGenRegisterInfo.inc"

5
lib/Target/Sparc/CMakeLists.txt
View File

@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS Sparc.td)
tablegen(SparcGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(SparcGenRegisterNames.inc -gen-register-enums)
tablegen(SparcGenRegisterInfo.inc -gen-register-desc)
tablegen(SparcGenRegisterDesc.inc -gen-register-desc)
tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(SparcGenRegisterInfo.inc -gen-register-info)
tablegen(SparcGenInstrNames.inc -gen-instr-enums)
tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
tablegen(SparcGenAsmWriter.inc -gen-asm-writer)

3
lib/Target/Sparc/Makefile
View File

@ -13,7 +13,8 @@ TARGET = Sparc
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \
SparcGenInstrNames.inc \
SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc

8
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -23,11 +23,14 @@
#include "llvm/Type.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "SparcGenRegisterDesc.inc"
#include "SparcGenRegisterInfo.inc"
using namespace llvm;
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
const TargetInstrInfo &tii)
: SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
: SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc,
SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
Subtarget(st), TII(tii) {
}
@ -135,6 +138,3 @@ int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
#include "SparcGenRegisterInfo.inc"

5
lib/Target/SystemZ/CMakeLists.txt
View File

@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS SystemZ.td)
tablegen(SystemZGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(SystemZGenRegisterNames.inc -gen-register-enums)
tablegen(SystemZGenRegisterInfo.inc -gen-register-desc)
tablegen(SystemZGenRegisterDesc.inc -gen-register-desc)
tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)

3
lib/Target/SystemZ/Makefile
View File

@ -13,7 +13,8 @@ TARGET = SystemZ
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \
SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \
SystemZGenInstrNames.inc \
SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc

8
lib/Target/SystemZ/SystemZRegisterInfo.cpp
View File

@ -25,11 +25,14 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/BitVector.h"
#include "SystemZGenRegisterDesc.inc"
#include "SystemZGenRegisterInfo.inc"
using namespace llvm;
SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
const SystemZInstrInfo &tii)
: SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
: SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc,
SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
TM(tm), TII(tii) {
}
@ -153,6 +156,3 @@ int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
assert(0 && "What is the dwarf register number");
return -1;
}
#include "SystemZGenRegisterInfo.inc"

9
lib/Target/TargetRegisterInfo.cpp
View File

@ -20,15 +20,12 @@
using namespace llvm;
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
regclass_iterator RCB, regclass_iterator RCE,
const char *const *subregindexnames,
int CFSO, int CFDO)
: Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
: InfoDesc(ID), SubRegIndexNames(subregindexnames),
RegClassBegin(RCB), RegClassEnd(RCE) {
assert(isPhysicalRegister(NumRegs) &&
"Target has too many physical registers!");
CallFrameSetupOpcode = CFSO;
CallFrameDestroyOpcode = CFDO;
}
@ -86,7 +83,7 @@ static void getAllocatableSetForRC(const MachineFunction &MF,
BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
const TargetRegisterClass *RC) const {
BitVector Allocatable(NumRegs);
BitVector Allocatable(getNumRegs());
if (RC) {
getAllocatableSetForRC(MF, RC, Allocatable);
} else {

5
lib/Target/X86/CMakeLists.txt
View File

@ -1,8 +1,9 @@
set(LLVM_TARGET_DEFINITIONS X86.td)
tablegen(X86GenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(X86GenRegisterNames.inc -gen-register-enums)
tablegen(X86GenRegisterInfo.inc -gen-register-desc)
tablegen(X86GenRegisterDesc.inc -gen-register-desc)
tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header)
tablegen(X86GenRegisterInfo.inc -gen-register-info)
tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
tablegen(X86GenInstrNames.inc -gen-instr-enums)
tablegen(X86GenInstrInfo.inc -gen-instr-desc)

9
lib/Target/X86/Makefile
View File

@ -12,14 +12,15 @@ LIBRARYNAME = LLVMX86CodeGen
TARGET = X86
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
X86GenRegisterInfo.inc X86GenInstrNames.inc \
X86GenInstrInfo.inc X86GenAsmWriter.inc X86GenAsmMatcher.inc \
BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \
X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \
X86GenInstrNames.inc X86GenInstrInfo.inc \
X86GenAsmWriter.inc X86GenAsmMatcher.inc \
X86GenAsmWriter1.inc X86GenDAGISel.inc \
X86GenDisassemblerTables.inc X86GenFastISel.inc \
X86GenCallingConv.inc X86GenSubtarget.inc \
X86GenEDInfo.inc
DIRS = InstPrinter AsmParser Disassembler TargetInfo Utils
DIRS = InstPrinter AsmParser Disassembler TargetInfo TargetDesc Utils
include $(LEVEL)/Makefile.common

16
lib/Target/X86/TargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/X86/TargetDesc/Makefile ------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMX86Desc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

23
lib/Target/X86/TargetDesc/X86TargetDesc.cpp Normal file
View File

@ -0,0 +1,23 @@
//===-- X86TargetDesc.cpp - X86 Target Descriptions -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides X86 specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "X86TargetDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "X86GenRegisterDesc.inc"
using namespace llvm;
MCRegisterInfo *createX86MCRegisterInfo() {
MCRegisterInfo *X = new MCRegisterInfo();
InitX86MCRegisterInfo(X);
return X;
}

17
lib/Target/X86/TargetDesc/X86TargetDesc.h Normal file
View File

@ -0,0 +1,17 @@
//===-- X86TargetDesc.h - X86 Target Descriptions ---------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides X86 specific target descriptions.
//
//===----------------------------------------------------------------------===//
// Defines symbolic names for X86 registers. This defines a mapping from
// register name to register number.
//
#include "X86GenRegisterNames.inc"

5
lib/Target/X86/X86.h
View File

@ -88,10 +88,7 @@ extern Target TheX86_32Target, TheX86_64Target;
} // End llvm namespace
// Defines symbolic names for X86 registers. This defines a mapping from
// register name to register number.
//
#include "X86GenRegisterNames.inc"
#include "TargetDesc/X86TargetDesc.h"
// Defines symbolic names for the X86 instructions.
//

7
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -39,6 +39,8 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/CommandLine.h"
#include "X86GenRegisterDesc.inc"
#include "X86GenRegisterInfo.inc"
using namespace llvm;
cl::opt<bool>
@ -49,7 +51,8 @@ ForceStackAlign("force-align-stack",
X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
const TargetInstrInfo &tii)
: X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
: X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc,
tm.getSubtarget<X86Subtarget>().is64Bit() ?
X86::ADJCALLSTACKDOWN64 :
X86::ADJCALLSTACKDOWN32,
tm.getSubtarget<X86Subtarget>().is64Bit() ?
@ -918,8 +921,6 @@ unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
}
}
#include "X86GenRegisterInfo.inc"
namespace {
struct MSAH : public MachineFunctionPass {
static char ID;

6
lib/Target/XCore/CMakeLists.txt
View File

@ -1,8 +1,8 @@
set(LLVM_TARGET_DEFINITIONS XCore.td)
tablegen(XCoreGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(XCoreGenRegisterNames.inc -gen-register-enums)
tablegen(XCoreGenRegisterInfo.inc -gen-register-desc)
tablegen(XCoreGenRegisterDesc.inc -gen-register-desc)
tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)

3
lib/Target/XCore/Makefile
View File

@ -13,7 +13,8 @@ TARGET = XCore
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \
XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \
XCoreGenInstrNames.inc \
XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
XCoreGenSubtarget.inc

9
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -32,11 +32,13 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "XCoreGenRegisterDesc.inc"
#include "XCoreGenRegisterInfo.inc"
using namespace llvm;
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
: XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
: XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc,
XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
TII(tii) {
}
@ -328,6 +330,3 @@ unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
unsigned XCoreRegisterInfo::getRARegister() const {
return XCore::LR;
}
#include "XCoreGenRegisterInfo.inc"

185
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -79,7 +79,8 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
<< " explicit " << ClassName
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
<< "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const;\n"
<< " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
@ -140,8 +141,6 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
CodeGenTarget Target(Records);
CodeGenRegBank &RegBank = Target.getRegBank();
RegBank.computeDerivedInfo();
std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
RegBank.computeOverlaps(Overlaps);
EmitSourceFileHeader("Register Information Source Fragment", OS);
@ -407,78 +406,22 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
<< "RegClass,\n";
OS << " };\n";
typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
// Emit extra information about registers.
OS << "\n static const TargetRegisterInfoDesc "
<< Target.getName() << "RegInfoDesc[] = "
<< "{ // Extra Descriptors\n";
OS << " { 0, 0 },\n";
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
// Emit an overlap list for all registers.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = Regs[i];
const CodeGenRegister::Set &O = Overlaps[Reg];
// Move Reg to the front so TRI::getAliasSet can share the list.
OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
<< getQualifiedName(Reg->TheDef) << ", ";
for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
I != E; ++I)
if (*I != Reg)
OS << getQualifiedName((*I)->TheDef) << ", ";
OS << "0 };\n";
}
// Emit the empty sub-registers list
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
// Loop over all of the registers which have sub-registers, emitting the
// sub-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
if (Reg.getSubRegs().empty())
continue;
// getSubRegs() orders by SubRegIndex. We want a topological order.
SetVector<CodeGenRegister*> SR;
Reg.addSubRegsPreOrder(SR);
OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
OS << "0 };\n";
}
// Emit the empty super-registers list
OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
// Loop over all of the registers which have super-registers, emitting the
// super-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
if (SR.empty())
continue;
OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
OS << "0 };\n";
}
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
OS << " { \"NOREG\",\t0,\t0,\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
OS << " { \"";
OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
if (!Reg.getSubRegs().empty())
OS << Reg.getName() << "_SubRegsSet,\t";
else
OS << "Empty_SubRegsSet,\t";
if (!Reg.getSuperRegs().empty())
OS << Reg.getName() << "_SuperRegsSet,\t";
else
OS << "Empty_SuperRegsSet,\t";
OS << Reg.CostPerUse << ",\t"
OS << " { ";
OS << Reg.CostPerUse << ", "
<< int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
}
OS << " };\n"; // End of register descriptors...
// Calculate the mapping of subregister+index pairs to physical registers.
// This will also create further anonymous indexes.
unsigned NamedIndices = RegBank.getNumNamedIndices();
@ -575,14 +518,18 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// Emit the constructor of the class...
OS << ClassName << "::" << ClassName
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
<< " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
<< "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
<< "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
<< " : TargetRegisterInfo(ID"
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
<< " SubRegIndexTable,\n"
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n"
<< " InitMCRegisterInfo(D, " << Regs.size()+1 << ");\n"
<< "}\n\n";
// Collect all information about dwarf register numbers
typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
// First, just pull all provided information to the map
unsigned maxLength = 0;
@ -671,3 +618,101 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
OS << "} // End llvm namespace \n";
}
void RegisterInfoEmitter::runDesc(raw_ostream &OS) {
CodeGenTarget Target(Records);
CodeGenRegBank &RegBank = Target.getRegBank();
RegBank.computeDerivedInfo();
std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
RegBank.computeOverlaps(Overlaps);
OS << "namespace llvm {\n\n";
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenMCRegisterInfo";
OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
<< " explicit " << ClassName << "(const TargetRegisterDesc *D);\n";
OS << "};\n";
OS << "\nnamespace {\n";
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
// Emit an overlap list for all registers.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = Regs[i];
const CodeGenRegister::Set &O = Overlaps[Reg];
// Move Reg to the front so TRI::getAliasSet can share the list.
OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
<< getQualifiedName(Reg->TheDef) << ", ";
for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
I != E; ++I)
if (*I != Reg)
OS << getQualifiedName((*I)->TheDef) << ", ";
OS << "0 };\n";
}
// Emit the empty sub-registers list
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
// Loop over all of the registers which have sub-registers, emitting the
// sub-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
if (Reg.getSubRegs().empty())
continue;
// getSubRegs() orders by SubRegIndex. We want a topological order.
SetVector<CodeGenRegister*> SR;
Reg.addSubRegsPreOrder(SR);
OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
OS << "0 };\n";
}
// Emit the empty super-registers list
OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
// Loop over all of the registers which have super-registers, emitting the
// super-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
if (SR.empty())
continue;
OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
OS << "0 };\n";
}
OS << "\n const TargetRegisterDesc " << TargetName
<< "RegDesc[] = { // Descriptors\n";
OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
OS << " { \"";
OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
if (!Reg.getSubRegs().empty())
OS << Reg.getName() << "_SubRegsSet,\t";
else
OS << "Empty_SubRegsSet,\t";
if (!Reg.getSuperRegs().empty())
OS << Reg.getName() << "_SuperRegsSet";
else
OS << "Empty_SuperRegsSet";
OS << " },\n";
}
OS << " };\n"; // End of register descriptors...
OS << "}\n\n"; // End of anonymous namespace...
// MCRegisterInfo initialization routine.
OS << "void " << "Init" << TargetName
<< "MCRegisterInfo(MCRegisterInfo *RI) {\n";
OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ");\n}\n\n";
OS << "} // End llvm namespace \n";
}

3
utils/TableGen/RegisterInfoEmitter.h
View File

@ -33,6 +33,9 @@ public:
// runEnums - Print out enum values for all of the registers.
void runEnums(raw_ostream &o);
// runDesc - Print out register descriptions.
void runDesc(raw_ostream &o);
};
} // End llvm namespace

20
utils/TableGen/TableGen.cpp
View File

@ -54,7 +54,7 @@ using namespace llvm;
enum ActionType {
PrintRecords,
GenEmitter,
GenRegisterEnums, GenRegister, GenRegisterHeader,
GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
GenARMDecoder,
GenDisassembler,
@ -95,10 +95,12 @@ namespace {
"Generate machine code emitter"),
clEnumValN(GenRegisterEnums, "gen-register-enums",
"Generate enum values for registers"),
clEnumValN(GenRegister, "gen-register-desc",
"Generate a register info description"),
clEnumValN(GenRegisterHeader, "gen-register-desc-header",
"Generate a register info description header"),
clEnumValN(GenRegisterDesc, "gen-register-desc",
"Generate register descriptions"),
clEnumValN(GenRegisterInfo, "gen-register-info",
"Generate registers & reg-classes info"),
clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
"Generate registers & reg-classes info header"),
clEnumValN(GenInstrEnums, "gen-instr-enums",
"Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc",
@ -261,14 +263,16 @@ int main(int argc, char **argv) {
case GenEmitter:
CodeEmitterGen(Records).run(Out.os());
break;
case GenRegisterEnums:
RegisterInfoEmitter(Records).runEnums(Out.os());
break;
case GenRegister:
case GenRegisterDesc:
RegisterInfoEmitter(Records).runDesc(Out.os());
break;
case GenRegisterInfo:
RegisterInfoEmitter(Records).run(Out.os());
break;
case GenRegisterHeader:
case GenRegisterInfoHeader:
RegisterInfoEmitter(Records).runHeader(Out.os());
break;
case GenInstrEnums: