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a347f85dbe
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
815 B
Makefile
26 lines
815 B
Makefile
##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file is distributed under the University of Illinois Open Source
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# License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = LLVMMipsCodeGen
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TARGET = Mips
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
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MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
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MipsGenInstrNames.inc \
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MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
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MipsGenDAGISel.inc MipsGenCallingConv.inc \
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MipsGenSubtarget.inc
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DIRS = TargetInfo
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include $(LEVEL)/Makefile.common
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