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AMDGPU: Fix not respecting byval alignment in call frame setup
This was hackily adding in the 4-bytes reserved for the callee's emergency stack slot. Treat it like a normal stack allocation so we get the correct alignment padding behavior. This fixes an inconsistency between the caller and callee. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340396 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
4d6d5a12e8
commit
ad45fb5af4
@ -4003,13 +4003,12 @@ SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
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SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
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const SDLoc &SL,
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SDValue Chain,
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SDValue StackPtr,
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SDValue ArgVal,
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int64_t Offset) const {
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MachineFunction &MF = DAG.getMachineFunction();
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MachinePointerInfo DstInfo = MachinePointerInfo::getStack(MF, Offset);
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SDValue Ptr = DAG.getObjectPtrOffset(SL, StackPtr, Offset);
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SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32);
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SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, 4,
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MachineMemOperand::MODereferenceable);
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return Store;
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@ -287,7 +287,6 @@ public:
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SDValue storeStackInputValue(SelectionDAG &DAG,
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const SDLoc &SL,
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SDValue Chain,
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SDValue StackPtr,
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SDValue ArgVal,
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int64_t Offset) const;
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@ -2181,11 +2181,11 @@ SDValue SITargetLowering::LowerCallResult(
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// from the explicit user arguments present in the IR.
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void SITargetLowering::passSpecialInputs(
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CallLoweringInfo &CLI,
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CCState &CCInfo,
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const SIMachineFunctionInfo &Info,
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SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
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SmallVectorImpl<SDValue> &MemOpChains,
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SDValue Chain,
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SDValue StackPtr) const {
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SDValue Chain) const {
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// If we don't have a call site, this was a call inserted by
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// legalization. These can never use special inputs.
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if (!CLI.CS)
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@ -2253,9 +2253,9 @@ void SITargetLowering::passSpecialInputs(
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if (OutgoingArg->isRegister()) {
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RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
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} else {
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SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, StackPtr,
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InputReg,
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OutgoingArg->getStackOffset());
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unsigned SpecialArgOffset = CCInfo.AllocateStack(ArgVT.getStoreSize(), 4);
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SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
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SpecialArgOffset);
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MemOpChains.push_back(ArgStore);
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}
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}
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@ -2401,8 +2401,6 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
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}
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// The first 4 bytes are reserved for the callee's emergency stack slot.
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const unsigned CalleeUsableStackOffset = 4;
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if (IsTailCall) {
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IsTailCall = isEligibleForTailCallOptimization(
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Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
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@ -2441,6 +2439,10 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, IsVarArg);
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// The first 4 bytes are reserved for the callee's emergency stack slot.
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CCInfo.AllocateStack(4, 4);
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CCInfo.AnalyzeCallOperands(Outs, AssignFn);
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// Get a count of how many bytes are to be pushed on the stack.
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@ -2488,10 +2490,6 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
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}
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}
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// Stack pointer relative accesses are done by changing the offset SGPR. This
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// is just the VGPR offset component.
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SDValue StackPtr = DAG.getConstant(CalleeUsableStackOffset, DL, MVT::i32);
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SmallVector<SDValue, 8> MemOpChains;
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MVT PtrVT = MVT::i32;
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@ -2535,7 +2533,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
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unsigned LocMemOffset = VA.getLocMemOffset();
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int32_t Offset = LocMemOffset;
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SDValue PtrOff = DAG.getObjectPtrOffset(DL, StackPtr, Offset);
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SDValue PtrOff = DAG.getConstant(Offset, DL, PtrVT);
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if (IsTailCall) {
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ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
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@ -2545,8 +2543,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
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Offset = Offset + FPDiff;
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int FI = MFI.CreateFixedObject(OpSize, Offset, true);
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DstAddr = DAG.getObjectPtrOffset(DL, DAG.getFrameIndex(FI, PtrVT),
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StackPtr);
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DstAddr = DAG.getFrameIndex(FI, PtrVT);
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DstInfo = MachinePointerInfo::getFixedStack(MF, FI);
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// Make sure any stack arguments overlapping with where we're storing
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@ -2581,7 +2578,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
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}
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// Copy special input registers after user input arguments.
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passSpecialInputs(CLI, *Info, RegsToPass, MemOpChains, Chain, StackPtr);
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passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
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@ -265,11 +265,11 @@ public:
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void passSpecialInputs(
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CallLoweringInfo &CLI,
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CCState &CCInfo,
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const SIMachineFunctionInfo &Info,
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SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
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SmallVectorImpl<SDValue> &MemOpChains,
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SDValue Chain,
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SDValue StackPtr) const;
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SDValue Chain) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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@ -110,7 +110,7 @@ entry:
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; GCN: s_sub_u32 s32, s32, 0xc00{{$}}
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @call_void_func_byval_struct_func() #0 {
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define void @call_void_func_byval_struct_func() #1 {
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entry:
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%arg0 = alloca %struct.ByValStruct, align 4, addrspace(5)
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%arg1 = alloca %struct.ByValStruct, align 4, addrspace(5)
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@ -163,7 +163,7 @@ entry:
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; GCN: s_swappc_b64
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; GCN-NOT: s_sub_u32 s32
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; GCN: s_endpgm
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define amdgpu_kernel void @call_void_func_byval_struct_kernel() #0 {
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define amdgpu_kernel void @call_void_func_byval_struct_kernel() #1 {
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entry:
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%arg0 = alloca %struct.ByValStruct, align 4, addrspace(5)
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%arg1 = alloca %struct.ByValStruct, align 4, addrspace(5)
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@ -181,6 +181,146 @@ entry:
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ret void
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}
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; GCN-LABEL: {{^}}void_func_byval_struct_align8:
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; GCN: s_mov_b32 s5, s32
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; GCN: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s5 offset:8{{$}}
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; GCN-NOT: s32
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; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], s5 offset:8{{$}}
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; GCN-NOT: s32
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; GCN: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s5 offset:24{{$}}
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; GCN-NOT: s32
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; GCN: buffer_store_dword [[LOAD1]], off, s[0:3], s5 offset:24{{$}}
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; GCN-NOT: s32
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define void @void_func_byval_struct_align8(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 8 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 8 %arg1) #1 {
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entry:
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%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
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%tmp = load volatile i32, i32 addrspace(5)* %arrayidx, align 8
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%add = add nsw i32 %tmp, 1
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store volatile i32 %add, i32 addrspace(5)* %arrayidx, align 8
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%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
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%tmp1 = load volatile i32, i32 addrspace(5)* %arrayidx2, align 8
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%add3 = add nsw i32 %tmp1, 2
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store volatile i32 %add3, i32 addrspace(5)* %arrayidx2, align 8
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store volatile i32 9, i32 addrspace(1)* null, align 4
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ret void
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}
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; Make sure the byval alignment is respected in the call frame setup
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; GCN-LABEL: {{^}}call_void_func_byval_struct_align8_kernel:
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; GCN: s_mov_b32 s33, s7
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; GCN: s_add_u32 s32, s33, 0xc00{{$}}
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; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN-DAG: v_mov_b32_e32 [[THIRTEEN:v[0-9]+]], 13
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s33 offset:8
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; GCN: buffer_store_dword [[THIRTEEN]], off, s[0:3], s33 offset:24
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; GCN-NOT: s_add_u32 s32, s32, 0x800
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; GCN-DAG: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s33 offset:8
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; GCN-DAG: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s33 offset:12
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; GCN-DAG: buffer_load_dword [[LOAD2:v[0-9]+]], off, s[0:3], s33 offset:16
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; GCN-DAG: buffer_load_dword [[LOAD3:v[0-9]+]], off, s[0:3], s33 offset:20
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; GCN-DAG: buffer_store_dword [[LOAD0]], off, s[0:3], s32 offset:8{{$}}
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; GCN-DAG: buffer_store_dword [[LOAD1]], off, s[0:3], s32 offset:12
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; GCN-DAG: buffer_store_dword [[LOAD2]], off, s[0:3], s32 offset:16
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; GCN-DAG: buffer_store_dword [[LOAD3]], off, s[0:3], s32 offset:20
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; GCN-DAG: buffer_load_dword [[LOAD4:v[0-9]+]], off, s[0:3], s33 offset:24
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; GCN-DAG: buffer_load_dword [[LOAD5:v[0-9]+]], off, s[0:3], s33 offset:28
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; GCN-DAG: buffer_load_dword [[LOAD6:v[0-9]+]], off, s[0:3], s33 offset:32
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; GCN-DAG: buffer_load_dword [[LOAD7:v[0-9]+]], off, s[0:3], s33 offset:36
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; GCN-DAG: buffer_store_dword [[LOAD4]], off, s[0:3], s32 offset:24
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; GCN-DAG: buffer_store_dword [[LOAD5]], off, s[0:3], s32 offset:28
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; GCN-DAG: buffer_store_dword [[LOAD6]], off, s[0:3], s32 offset:32
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; GCN-DAG: buffer_store_dword [[LOAD7]], off, s[0:3], s32 offset:36
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; GCN: s_swappc_b64
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; GCN-NOT: s_sub_u32 s32
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; GCN: s_endpgm
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define amdgpu_kernel void @call_void_func_byval_struct_align8_kernel() #1 {
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entry:
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%arg0 = alloca %struct.ByValStruct, align 8, addrspace(5)
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%arg1 = alloca %struct.ByValStruct, align 8, addrspace(5)
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%tmp = bitcast %struct.ByValStruct addrspace(5)* %arg0 to i8 addrspace(5)*
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call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp)
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%tmp1 = bitcast %struct.ByValStruct addrspace(5)* %arg1 to i8 addrspace(5)*
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call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp1)
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%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
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store volatile i32 9, i32 addrspace(5)* %arrayidx, align 8
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%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
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store volatile i32 13, i32 addrspace(5)* %arrayidx2, align 8
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call void @void_func_byval_struct_align8(%struct.ByValStruct addrspace(5)* byval nonnull align 8 %arg0, %struct.ByValStruct addrspace(5)* byval nonnull align 8 %arg1)
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call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp1)
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call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp)
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ret void
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}
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; GCN-LABEL: {{^}}call_void_func_byval_struct_align8_func:
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; GCN: s_mov_b32 s5, s32
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; GCN-DAG: s_add_u32 s32, s32, 0xc00{{$}}
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; GCN-DAG: v_writelane_b32
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; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN-DAG: v_mov_b32_e32 [[THIRTEEN:v[0-9]+]], 13
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; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s5 offset:8
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; GCN-DAG: buffer_store_dword [[THIRTEEN]], off, s[0:3], s5 offset:24
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; GCN-DAG: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s5 offset:8
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; GCN-DAG: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s5 offset:12
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; GCN-DAG: buffer_load_dword [[LOAD2:v[0-9]+]], off, s[0:3], s5 offset:16
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; GCN-DAG: buffer_load_dword [[LOAD3:v[0-9]+]], off, s[0:3], s5 offset:20
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; GCN-NOT: s_add_u32 s32, s32, 0x800
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; GCN-DAG: buffer_store_dword [[LOAD0]], off, s[0:3], s32 offset:8{{$}}
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; GCN-DAG: buffer_store_dword [[LOAD1]], off, s[0:3], s32 offset:12
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; GCN-DAG: buffer_store_dword [[LOAD2]], off, s[0:3], s32 offset:16
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; GCN-DAG: buffer_store_dword [[LOAD3]], off, s[0:3], s32 offset:20
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; GCN: buffer_load_dword [[LOAD4:v[0-9]+]], off, s[0:3], s5 offset:24
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; GCN: buffer_load_dword [[LOAD5:v[0-9]+]], off, s[0:3], s5 offset:28
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; GCN: buffer_load_dword [[LOAD6:v[0-9]+]], off, s[0:3], s5 offset:32
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; GCN: buffer_load_dword [[LOAD7:v[0-9]+]], off, s[0:3], s5 offset:36
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; GCN-DAG: buffer_store_dword [[LOAD4]], off, s[0:3], s32 offset:24
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; GCN-DAG: buffer_store_dword [[LOAD5]], off, s[0:3], s32 offset:28
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; GCN-DAG: buffer_store_dword [[LOAD6]], off, s[0:3], s32 offset:32
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; GCN-DAG: buffer_store_dword [[LOAD7]], off, s[0:3], s32 offset:36
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; GCN: s_swappc_b64
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; GCN-NOT: v_readlane_b32 s32
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; GCN: v_readlane_b32
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; GCN-NOT: v_readlane_b32 s32
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; GCN-NOT: s_sub_u32 s32, s32, 0x800
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; GCN: s_sub_u32 s32, s32, 0xc00{{$}}
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @call_void_func_byval_struct_align8_func() #0 {
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entry:
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%arg0 = alloca %struct.ByValStruct, align 8, addrspace(5)
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%arg1 = alloca %struct.ByValStruct, align 8, addrspace(5)
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%tmp = bitcast %struct.ByValStruct addrspace(5)* %arg0 to i8 addrspace(5)*
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call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp)
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%tmp1 = bitcast %struct.ByValStruct addrspace(5)* %arg1 to i8 addrspace(5)*
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call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp1)
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%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
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store volatile i32 9, i32 addrspace(5)* %arrayidx, align 8
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%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
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store volatile i32 13, i32 addrspace(5)* %arrayidx2, align 8
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call void @void_func_byval_struct_align8(%struct.ByValStruct addrspace(5)* byval nonnull align 8 %arg0, %struct.ByValStruct addrspace(5)* byval nonnull align 8 %arg1)
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call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp1)
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call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp)
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ret void
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}
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; GCN-LABEL: {{^}}call_void_func_byval_struct_kernel_no_frame_pointer_elim:
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define amdgpu_kernel void @call_void_func_byval_struct_kernel_no_frame_pointer_elim() #2 {
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entry:
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@ -290,7 +290,7 @@ define void @too_many_args_use_workitem_id_x(
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; GCN: s_mov_b32 s33, s7
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; GCN: s_mov_b32 s32, s33
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; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:8
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; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:4
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; GCN: s_mov_b32 s4, s33
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x() #1 {
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@ -308,7 +308,7 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x() #1 {
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; GCN-LABEL: {{^}}func_call_too_many_args_use_workitem_id_x:
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; GCN: s_mov_b32 s5, s32
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; GCN: buffer_store_dword v1, off, s[0:3], s32 offset:8
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; GCN: buffer_store_dword v1, off, s[0:3], s32 offset:
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; GCN: s_swappc_b64
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define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
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store volatile i32 %arg0, i32 addrspace(1)* undef
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@ -330,7 +330,7 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
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; GCN: s_add_u32 s32, s32, 0x400{{$}}
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; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:4
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; GCN: buffer_store_dword v32, off, s[0:3], s32 offset:8{{$}}
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; GCN: buffer_store_dword v32, off, s[0:3], s32 offset:4{{$}}
|
||||
|
||||
; GCN: s_swappc_b64
|
||||
|
||||
@ -428,7 +428,7 @@ define void @too_many_args_use_workitem_id_x_byval(
|
||||
; GCN-NOT: s32
|
||||
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
|
||||
; GCN: buffer_store_dword [[K]], off, s[0:3], s33 offset:4
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:12
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:8
|
||||
|
||||
; GCN: buffer_load_dword [[RELOAD_BYVAL:v[0-9]+]], off, s[0:3], s33 offset:4
|
||||
; GCN: buffer_store_dword [[RELOAD_BYVAL]], off, s[0:3], s32 offset:4{{$}}
|
||||
@ -453,7 +453,7 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1
|
||||
; GCN-LABEL: {{^}}func_call_too_many_args_use_workitem_id_x_byval:
|
||||
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
|
||||
; GCN: buffer_store_dword [[K]], off, s[0:3], s5 offset:4
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:12
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:8
|
||||
|
||||
; GCN: buffer_load_dword [[RELOAD_BYVAL:v[0-9]+]], off, s[0:3], s5 offset:4
|
||||
; GCN: buffer_store_dword [[RELOAD_BYVAL]], off, s[0:3], s32 offset:4{{$}}
|
||||
@ -539,11 +539,10 @@ define void @too_many_args_use_workitem_id_xyz(
|
||||
ret void
|
||||
}
|
||||
|
||||
; frame[0] = kernel emergency stack slot
|
||||
; frame[1] = callee emergency stack slot
|
||||
; frame[2] = ID X
|
||||
; frame[3] = ID Y
|
||||
; frame[4] = ID Z
|
||||
; frame[0] = callee emergency stack slot
|
||||
; frame[1] = ID X
|
||||
; frame[2] = ID Y
|
||||
; frame[3] = ID Z
|
||||
|
||||
; GCN-LABEL: {{^}}kern_call_too_many_args_use_workitem_id_xyz:
|
||||
; GCN: enable_vgpr_workitem_id = 2
|
||||
@ -551,9 +550,9 @@ define void @too_many_args_use_workitem_id_xyz(
|
||||
; GCN: s_mov_b32 s33, s7
|
||||
; GCN: s_mov_b32 s32, s33
|
||||
|
||||
; GCN-DAG: buffer_store_dword v0, off, s[0:3], s32 offset:8
|
||||
; GCN-DAG: buffer_store_dword v1, off, s[0:3], s32 offset:12
|
||||
; GCN-DAG: buffer_store_dword v2, off, s[0:3], s32 offset:16
|
||||
; GCN-DAG: buffer_store_dword v0, off, s[0:3], s32 offset:4
|
||||
; GCN-DAG: buffer_store_dword v1, off, s[0:3], s32 offset:8
|
||||
; GCN-DAG: buffer_store_dword v2, off, s[0:3], s32 offset:12
|
||||
; GCN: s_swappc_b64
|
||||
define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_xyz() #1 {
|
||||
call void @too_many_args_use_workitem_id_xyz(
|
||||
@ -635,10 +634,9 @@ define void @too_many_args_use_workitem_id_x_stack_yz(
|
||||
ret void
|
||||
}
|
||||
|
||||
; frame[0] = kernel emergency stack slot
|
||||
; frame[1] = callee emergency stack slot
|
||||
; frame[2] = ID Y
|
||||
; frame[3] = ID Z
|
||||
; frame[0] = callee emergency stack slot
|
||||
; frame[1] = ID Y
|
||||
; frame[2] = ID Z
|
||||
|
||||
; GCN-LABEL: {{^}}kern_call_too_many_args_use_workitem_id_x_stack_yz:
|
||||
; GCN: enable_vgpr_workitem_id = 2
|
||||
@ -647,8 +645,8 @@ define void @too_many_args_use_workitem_id_x_stack_yz(
|
||||
; GCN: s_mov_b32 s32, s33
|
||||
|
||||
; GCN-DAG: v_mov_b32_e32 v31, v0
|
||||
; GCN-DAG: buffer_store_dword v1, off, s[0:3], s32 offset:8
|
||||
; GCN-DAG: buffer_store_dword v2, off, s[0:3], s32 offset:12
|
||||
; GCN-DAG: buffer_store_dword v1, off, s[0:3], s32 offset:4
|
||||
; GCN-DAG: buffer_store_dword v2, off, s[0:3], s32 offset:8
|
||||
; GCN: s_swappc_b64
|
||||
define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_stack_yz() #1 {
|
||||
call void @too_many_args_use_workitem_id_x_stack_yz(
|
||||
|
||||
Loading…
Reference in New Issue
Block a user