gn build: add Hexagon target

Differential Revision: https://reviews.llvm.org/D61819

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360647 91177308-0d34-0410-b5e6-96231b3b80d8

utils/gn/secondary/llvm/lib/Target/Hexagon/AsmParser/BUILD.gn

@@ -0,0 +1,22 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("HexagonGenAsmMatcher") {
+  visibility = [ ":AsmParser" ]
+  args = [ "-gen-asm-matcher" ]
+  td_file = "../Hexagon.td"
+}
+
+static_library("AsmParser") {
+  output_name = "LLVMHexagonAsmParser"
+  deps = [
+    ":HexagonGenAsmMatcher",
+    "//llvm/lib/MC",
+    "//llvm/lib/MC/MCParser",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/Hexagon/MCTargetDesc",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "HexagonAsmParser.cpp",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn

@@ -0,0 +1,112 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("HexagonGenCallingConv") {
+  visibility = [ ":LLVMHexagonCodeGen" ]
+  args = [ "-gen-callingconv" ]
+  td_file = "Hexagon.td"
+}
+
+tablegen("HexagonGenDAGISel") {
+  visibility = [ ":LLVMHexagonCodeGen" ]
+  args = [ "-gen-dag-isel" ]
+  td_file = "Hexagon.td"
+}
+
+tablegen("HexagonGenDFAPacketizer") {
+  visibility = [ ":LLVMHexagonCodeGen" ]
+  args = [ "-gen-dfa-packetizer" ]
+  td_file = "Hexagon.td"
+}
+
+static_library("LLVMHexagonCodeGen") {
+  deps = [
+    ":HexagonGenCallingConv",
+    ":HexagonGenDAGISel",
+    ":HexagonGenDFAPacketizer",
+    "MCTargetDesc",
+    "TargetInfo",
+    "//llvm/include/llvm/Config:llvm-config",
+    "//llvm/lib/Analysis",
+    "//llvm/lib/CodeGen",
+    "//llvm/lib/CodeGen/AsmPrinter",
+    "//llvm/lib/CodeGen/SelectionDAG",
+    "//llvm/lib/IR",
+    "//llvm/lib/MC",
+    "//llvm/lib/Passes",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target",
+    "//llvm/lib/Transforms/Utils",
+  ]
+  include_dirs = [ "." ]
+  sources = [
+    "BitTracker.cpp",
+    "HexagonAsmPrinter.cpp",
+    "HexagonBitSimplify.cpp",
+    "HexagonBitTracker.cpp",
+    "HexagonBlockRanges.cpp",
+    "HexagonBranchRelaxation.cpp",
+    "HexagonCFGOptimizer.cpp",
+    "HexagonCommonGEP.cpp",
+    "HexagonConstExtenders.cpp",
+    "HexagonConstPropagation.cpp",
+    "HexagonCopyToCombine.cpp",
+    "HexagonEarlyIfConv.cpp",
+    "HexagonExpandCondsets.cpp",
+    "HexagonFixupHwLoops.cpp",
+    "HexagonFrameLowering.cpp",
+    "HexagonGenExtract.cpp",
+    "HexagonGenInsert.cpp",
+    "HexagonGenMux.cpp",
+    "HexagonGenPredicate.cpp",
+    "HexagonHardwareLoops.cpp",
+    "HexagonHazardRecognizer.cpp",
+    "HexagonInstrInfo.cpp",
+    "HexagonISelDAGToDAG.cpp",
+    "HexagonISelDAGToDAGHVX.cpp",
+    "HexagonISelLowering.cpp",
+    "HexagonISelLoweringHVX.cpp",
+    "HexagonLoopIdiomRecognition.cpp",
+    "HexagonMachineFunctionInfo.cpp",
+    "HexagonMachineScheduler.cpp",
+    "HexagonMCInstLower.cpp",
+    "HexagonNewValueJump.cpp",
+    "HexagonOptAddrMode.cpp",
+    "HexagonOptimizeSZextends.cpp",
+    "HexagonPeephole.cpp",
+    "HexagonRDFOpt.cpp",
+    "HexagonRegisterInfo.cpp",
+    "HexagonSelectionDAGInfo.cpp",
+    "HexagonSplitConst32AndConst64.cpp",
+    "HexagonSplitDouble.cpp",
+    "HexagonStoreWidening.cpp",
+    "HexagonSubtarget.cpp",
+    "HexagonTargetMachine.cpp",
+    "HexagonTargetObjectFile.cpp",
+    "HexagonTargetTransformInfo.cpp",
+    "HexagonVectorLoopCarriedReuse.cpp",
+    "HexagonVectorPrint.cpp",
+    "HexagonVExtract.cpp",
+    "HexagonVLIWPacketizer.cpp",
+    "RDFCopy.cpp",
+    "RDFDeadCode.cpp",
+    "RDFGraph.cpp",
+    "RDFLiveness.cpp",
+    "RDFRegisters.cpp",
+  ]
+}
+
+# This is a bit different from most build files: Due to this group
+# having the directory's name, "//llvm/lib/Target/Hexagon" will refer to this
+# target, which pulls in the code in this directory *and all subdirectories*.
+# For most other directories, "//llvm/lib/Foo" only pulls in the code directly
+# in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this
+# different behavior.
+group("Hexagon") {
+  deps = [
+    ":LLVMHexagonCodeGen",
+    "AsmParser",
+    "Disassembler",
+    "MCTargetDesc",
+    "TargetInfo",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/Hexagon/Disassembler/BUILD.gn

@@ -0,0 +1,22 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("HexagonGenDisassemblerTables") {
+  visibility = [ ":Disassembler" ]
+  args = [ "-gen-disassembler" ]
+  td_file = "../Hexagon.td"
+}
+
+static_library("Disassembler") {
+  output_name = "LLVMHexagonDisassembler"
+  deps = [
+    ":HexagonGenDisassemblerTables",
+    "//llvm/lib/MC/MCDisassembler",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/Hexagon/MCTargetDesc",
+    "//llvm/lib/Target/Hexagon/TargetInfo",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "HexagonDisassembler.cpp",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/Hexagon/MCTargetDesc/BUILD.gn

@@ -0,0 +1,74 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("HexagonGenAsmWriter") {
+  visibility = [ ":MCTargetDesc" ]
+  args = [ "-gen-asm-writer" ]
+  td_file = "../Hexagon.td"
+}
+
+tablegen("HexagonGenInstrInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-instr-info" ]
+  td_file = "../Hexagon.td"
+}
+
+tablegen("HexagonGenMCCodeEmitter") {
+  visibility = [ ":MCTargetDesc" ]
+  args = [ "-gen-emitter" ]
+  td_file = "../Hexagon.td"
+}
+
+tablegen("HexagonGenRegisterInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-register-info" ]
+  td_file = "../Hexagon.td"
+}
+
+tablegen("HexagonGenSubtargetInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-subtarget" ]
+  td_file = "../Hexagon.td"
+}
+
+group("tablegen") {
+  visibility = [
+    ":MCTargetDesc",
+    "../TargetInfo",
+  ]
+  public_deps = [
+    ":HexagonGenInstrInfo",
+    ":HexagonGenRegisterInfo",
+    ":HexagonGenSubtargetInfo",
+  ]
+}
+
+static_library("MCTargetDesc") {
+  output_name = "LLVMHexagonDesc"
+  public_deps = [
+    ":tablegen",
+  ]
+  deps = [
+    ":HexagonGenAsmWriter",
+    ":HexagonGenMCCodeEmitter",
+    "//llvm/lib/MC",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/Hexagon/TargetInfo",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "HexagonAsmBackend.cpp",
+    "HexagonELFObjectWriter.cpp",
+    "HexagonInstPrinter.cpp",
+    "HexagonMCAsmInfo.cpp",
+    "HexagonMCChecker.cpp",
+    "HexagonMCCodeEmitter.cpp",
+    "HexagonMCCompound.cpp",
+    "HexagonMCDuplexInfo.cpp",
+    "HexagonMCELFStreamer.cpp",
+    "HexagonMCExpr.cpp",
+    "HexagonMCInstrInfo.cpp",
+    "HexagonMCShuffler.cpp",
+    "HexagonMCTargetDesc.cpp",
+    "HexagonShuffler.cpp",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/Hexagon/TargetInfo/BUILD.gn

@@ -0,0 +1,15 @@
+static_library("TargetInfo") {
+  output_name = "LLVMHexagonInfo"
+  deps = [
+    "//llvm/lib/IR",
+    "//llvm/lib/Support",
+
+    # MCTargetDesc depends on TargetInfo, so we can't depend on the full
+    # MCTargetDesc target here: it would form a cycle.
+    "//llvm/lib/Target/Hexagon/MCTargetDesc:tablegen",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "HexagonTargetInfo.cpp",
+  ]
+}

utils/gn/secondary/llvm/lib/Target/targets.gni

@@ -23,6 +23,7 @@ if (llvm_targets_to_build == "host") {
     "AArch64",
     "ARM",
     "BPF",
+    "Hexagon",
     "Lanai",
     "PowerPC",
     "Sparc",
@@ -46,6 +47,8 @@ foreach(target, llvm_targets_to_build) {
     llvm_build_ARM = true
   } else if (target == "BPF") {
     llvm_build_BPF = true
+  } else if (target == "Hexagon") {
+    # Nothing to do.
   } else if (target == "Lanai") {
     # Nothing to do.
   } else if (target == "PowerPC") {