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[ARM] Fix parsing of special register masks

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This parsing code was incorrectly checking for invalid characters, so an
invalid instruction like:
  msr spsr_w, r0
would be emitted as:
  msr spsr_cxsf, r0

Differential revision: https://reviews.llvm.org/D30462



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296607 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Oliver Stannard
2017-03-01 10:51:04 +00:00
parent 145ace26f5
commit b6dfd8e2c3
2 changed files with 12 additions and 1 deletions
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lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+1 -1
View File
@@ -4330,7 +4330,7 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
// If some specific flag is already set, it means that some letter is
// present more than once, this is not acceptable.
if (FlagsVal == ~0U || (FlagsVal & Flag))
if (Flag == ~0U || (FlagsVal & Flag))
return MatchOperand_NoMatch;
FlagsVal |= Flag;
}
test/MC/ARM/invalid-special-reg.s
+11
View File
@@ -0,0 +1,11 @@
@ RUN: not llvm-mc -triple armv7a--none-eabi < %s |& FileCheck %s
@ RUN: not llvm-mc -triple thumbv7a--none-eabi < %s |& FileCheck %s
msr apsr_c, r0
@ CHECK: invalid operand for instruction
msr cpsr_w
@ CHECK: invalid operand for instruction
msr cpsr_cc
@ CHECK: invalid operand for instruction
msr xpsr_c
@ CHECK: invalid operand for instruction