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[AArch64] Add nvcast patterns for v2f32 -> v1f64

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Summary: Constant stores of f32 values can create such NvCast nodes.

Reviewers: t.p.northover

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62285

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361584 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Serge Pavlov
2019-05-24 01:20:34 +00:00
parent deeb5d51e3
commit c2bb63e2a3
2 changed files with 13 additions and 0 deletions
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lib/Target/AArch64/AArch64InstrInfo.td
+1
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@@ -6203,6 +6203,7 @@ def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
def : Pat<(v1f64 (AArch64NvCast (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
// Natural vector casts (128 bit)
def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
test/CodeGen/AArch64/arm64-nvcast.ll
+12
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@@ -47,3 +47,15 @@ entry:
store <2 x float> <float 0xC7DFDFDFC0000000, float 0xC7DFDFDFC0000000>, <2 x float>* bitcast (%"st1"* @_gv to <2 x float>*), align 8
ret void
}
%struct.Vector3 = type { float, float, float }
define void @nvcast_v2f32_v1f64(%struct.Vector3*) {
; CHECK-LABEL: _nvcast_v2f32_v1f64
; CHECK: fmov.2s v[[REG:[0-9]+]], #1.00000000
; CHECK: str d[[REG]], [x0]
entry:
%a13 = bitcast %struct.Vector3* %0 to <1 x double>*
store <1 x double> <double 0x3F8000003F800000>, <1 x double>* %a13, align 8
ret void
}