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Identity copies should not contribute to spill weight.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84978 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-10-23 23:09:19 +00:00
parent 7388037dd1
commit c9dfeb1be8
2 changed files with 28 additions and 4 deletions
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25
include/llvm/Target/TargetInstrInfo.h
View File

@ -133,13 +133,34 @@ private:
AliasAnalysis *AA) const; AliasAnalysis *AA) const;
public: public:
/// Return true if the instruction is a register to register move and return /// isMoveInstr - Return true if the instruction is a register to register
/// the source and dest operands and their sub-register indices by reference. /// move and return the source and dest operands and their sub-register
/// indices by reference.
virtual bool isMoveInstr(const MachineInstr& MI, virtual bool isMoveInstr(const MachineInstr& MI,
unsigned& SrcReg, unsigned& DstReg, unsigned& SrcReg, unsigned& DstReg,
unsigned& SrcSubIdx, unsigned& DstSubIdx) const { unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
return false; return false;
} }
/// isIdentityCopy - Return true if the instruction is a copy (or
/// extract_subreg, insert_subreg, subreg_to_reg) where the source and
/// destination registers are the same.
bool isIdentityCopy(const MachineInstr &MI) const {
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
SrcReg == DstReg)
return true;
if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
return true;
if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
return true;
return false;
}
/// isLoadFromStackSlot - If the specified machine instruction is a direct /// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of /// load from a stack slot, return the virtual or physical register number of

7
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -2556,6 +2556,7 @@ static bool isZeroLengthInterval(LiveInterval *li, LiveIntervals *li_) {
return true; return true;
} }
void SimpleRegisterCoalescing::CalculateSpillWeights() { void SimpleRegisterCoalescing::CalculateSpillWeights() {
SmallSet<unsigned, 4> Processed; SmallSet<unsigned, 4> Processed;
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
@ -2566,9 +2567,11 @@ void SimpleRegisterCoalescing::CalculateSpillWeights() {
unsigned loopDepth = loop ? loop->getLoopDepth() : 0; unsigned loopDepth = loop ? loop->getLoopDepth() : 0;
bool isExit = loop ? loop->isLoopExit(MBB) : false; bool isExit = loop ? loop->isLoopExit(MBB) : false;
for (MachineBasicBlock::iterator mii = MBB->begin(), mie = MBB->end(); for (MachineBasicBlock::const_iterator mii = MBB->begin(), mie = MBB->end();
mii != mie; ++mii) { mii != mie; ++mii) {
MachineInstr *MI = mii; const MachineInstr *MI = mii;
if (tii_->isIdentityCopy(*MI))
continue;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &mopi = MI->getOperand(i); const MachineOperand &mopi = MI->getOperand(i);