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ARM: correctly update CFG when splitting BB to fix branch.
Because the block-splitting code is multi-purpose, we have to meddle with the branches when using it to fixup a conditional branch destination. We got the code right, but forgot to update the CFG so the verifier complained when expensive checks were on. Probably harmless since constant-islands comes so late, but best to fix it anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318148 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1689,6 +1689,12 @@ ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
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int delta = TII->getInstSizeInBytes(MBB->back());
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BBInfo[MBB->getNumber()].Size -= delta;
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MBB->back().eraseFromParent();
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// The conditional successor will be swapped between the BBs after this, so
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// update CFG.
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MBB->addSuccessor(DestBB);
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std::next(MBB->getIterator())->removeSuccessor(DestBB);
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// BBInfo[SplitBB].Offset is wrong temporarily, fixed below
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}
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MachineBasicBlock *NextBB = &*++MBB->getIterator();
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64
test/CodeGen/ARM/constant-islands-cfg.mir
Normal file
64
test/CodeGen/ARM/constant-islands-cfg.mir
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@ -0,0 +1,64 @@
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# RUN: llc -mtriple=thumbv6m-apple-ios -run-pass=arm-cp-islands %s -o - | FileCheck %s
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--- |
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; Function Attrs: minsize nounwind optsize uwtable
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define arm_aapcscc double @test_split_cfg(double %a, double %b) local_unnamed_addr #0 {
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ret double undef
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}
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...
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---
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name: test_split_cfg
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '%r0', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 48
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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# CHECK-LABEL: name: test_split_cfg
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# CHECK: bb.0:
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# CHECK: successors: %[[LONG_BR_BB:bb.[0-9]+]](0x{{[0-9a-f]+}}), %[[DEST1:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
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# CHECK: tBcc %[[LONG_BR_BB]], 0, %cpsr
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# CHECK: tB %[[DEST1]]
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# CHECK: [[LONG_BR_BB]]:
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# CHECK: successors: %[[DEST2:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
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# CHECK: tB %[[DEST2]]
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# CHECK: [[DEST1]]:
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# CHECK: [[DEST2]]:
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body: |
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bb.0:
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liveins: %r0
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tCMPi8 killed %r0, 0, 14, _, implicit-def %cpsr
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tBcc %bb.2, 1, killed %cpsr
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tB %bb.3, 14, _
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bb.1:
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dead %r0 = SPACE 256, undef %r0
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bb.2:
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tPOP_RET 14, _, def %pc
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bb.3:
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tPOP_RET 14, _, def %pc
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...
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