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[ARM][NEON] Add support for ISD::ABS lowering

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Update NEON int_arm_neon_vabs intrinsic to use the ISD::ABS opcode directly

Added constant folding tests.

Differential Revision: https://reviews.llvm.org/D32938

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302417 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
2017-05-08 10:37:34 +00:00
parent b7c80c3cd2
commit cf3a86efe4
3 changed files with 43 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/Target/ARM/ARMISelLowering.cpp
+4 -1
View File
@@ -202,7 +202,7 @@ void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
if (!VT.isFloatingPoint() &&
VT != MVT::v2i64 && VT != MVT::v1i64)
for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
setOperationAction(Opcode, VT, Legal);
}
@@ -3316,6 +3316,9 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
}
return Result;
}
case Intrinsic::arm_neon_vabs:
return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
Op.getOperand(1));
case Intrinsic::arm_neon_vmulls:
case Intrinsic::arm_neon_vmullu: {
unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
lib/Target/ARM/ARMInstrNEON.td
+1 -25
View File
@@ -5558,8 +5558,7 @@ defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
// VABS : Vector Absolute Value
defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
int_arm_neon_vabs>;
IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s", abs>;
def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
"vabs", "f32",
v2f32, v2f32, fabs>;
@@ -5575,29 +5574,6 @@ def VABShq : N2VQ<0b11, 0b11, 0b01, 0b01, 0b01110, 0,
v8f16, v8f16, fabs>,
Requires<[HasNEON, HasFullFP16]>;
def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
(v2i32 (bitconvert (v8i8 (add DPR:$src,
(NEONvshrs DPR:$src, (i32 7))))))),
(VABSv8i8 DPR:$src)>;
def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
(v2i32 (bitconvert (v4i16 (add DPR:$src,
(NEONvshrs DPR:$src, (i32 15))))))),
(VABSv4i16 DPR:$src)>;
def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
(v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
(VABSv2i32 DPR:$src)>;
def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
(v4i32 (bitconvert (v16i8 (add QPR:$src,
(NEONvshrs QPR:$src, (i32 7))))))),
(VABSv16i8 QPR:$src)>;
def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
(v4i32 (bitconvert (v8i16 (add QPR:$src,
(NEONvshrs QPR:$src, (i32 15))))))),
(VABSv8i16 QPR:$src)>;
def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
(v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
(VABSv4i32 QPR:$src)>;
// VQABS : Vector Saturating Absolute Value
defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
test/CodeGen/ARM/vabs.ll
+38
View File
@@ -8,6 +8,22 @@ define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
ret <8 x i8> %tmp2
}
define <8 x i8> @vabss8_fold(<8 x i8>* %A) nounwind {
; CHECK-LABEL: vabss8_fold:
; CHECK: vldr d16, .LCPI1_0
; CHECK: .LCPI1_0:
; CHECK-NEXT: .byte 128 @ 0x80
; CHECK-NEXT: .byte 127 @ 0x7f
; CHECK-NEXT: .byte 1 @ 0x1
; CHECK-NEXT: .byte 0 @ 0x0
; CHECK-NEXT: .byte 1 @ 0x1
; CHECK-NEXT: .byte 127 @ 0x7f
; CHECK-NEXT: .byte 128 @ 0x80
; CHECK-NEXT: .byte 1 @ 0x1
%tmp1 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> <i8 -128, i8 -127, i8 -1, i8 0, i8 1, i8 127, i8 128, i8 255>)
ret <8 x i8> %tmp1
}
define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
;CHECK-LABEL: vabss16:
;CHECK: vabs.s16
@@ -16,6 +32,18 @@ define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
ret <4 x i16> %tmp2
}
define <4 x i16> @vabss16_fold() nounwind {
; CHECK-LABEL: vabss16_fold:
; CHECK: vldr d16, .LCPI3_0
; CHECK: .LCPI3_0:
; CHECK-NEXT: .short 32768 @ 0x8000
; CHECK-NEXT: .short 32767 @ 0x7fff
; CHECK-NEXT: .short 255 @ 0xff
; CHECK-NEXT: .short 32768 @ 0x8000
%tmp1 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> <i16 -32768, i16 -32767, i16 255, i16 32768>)
ret <4 x i16> %tmp1
}
define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
;CHECK-LABEL: vabss32:
;CHECK: vabs.s32
@@ -24,6 +52,16 @@ define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
ret <2 x i32> %tmp2
}
define <2 x i32> @vabss32_fold() nounwind {
; CHECK-LABEL: vabss32_fold:
; CHECK: vldr d16, .LCPI5_0
; CHECK: .LCPI5_0:
; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
; CHECK-NEXT: .long 2147483648 @ 0x80000000
%tmp1 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> <i32 -2147483647, i32 2147483648>)
ret <2 x i32> %tmp1
}
define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
;CHECK-LABEL: vabsf32:
;CHECK: vabs.f32