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[AVX-512] Add VLX command lines to 128 and 256-bit shufffle tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283014 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
@@ -2,8 +2,9 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1OR2 --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1OR2 --check-prefix=AVX2OR512VL --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx512vl,+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2OR512VL --check-prefix=AVX512VL
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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@@ -34,10 +35,10 @@ define <16 x i8> @shuffle_v16i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00(
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; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: shuffle_v16i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
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; AVX2-NEXT: retq
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; AVX2OR512VL-LABEL: shuffle_v16i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
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; AVX2OR512VL: # BB#0:
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; AVX2OR512VL-NEXT: vpbroadcastb %xmm0, %xmm0
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; AVX2OR512VL-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <16 x i8> %shuffle
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}
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@@ -60,10 +61,17 @@ define <16 x i8> @shuffle_v16i8_00_00_00_00_00_00_00_00_01_01_01_01_01_01_01_01(
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_00_00_00_00_00_00_00_00_01_01_01_01_01_01_01_01:
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; AVX: # BB#0:
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1]
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; AVX-NEXT: retq
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; AVX1OR2-LABEL: shuffle_v16i8_00_00_00_00_00_00_00_00_01_01_01_01_01_01_01_01:
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; AVX1OR2: # BB#0:
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; AVX1OR2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1]
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; AVX1OR2-NEXT: retq
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;
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; AVX512VL-LABEL: shuffle_v16i8_00_00_00_00_00_00_00_00_01_01_01_01_01_01_01_01:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; AVX512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,1,1,4,5,6,7]
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
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; AVX512VL-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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ret <16 x i8> %shuffle
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}
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@@ -88,10 +96,17 @@ define <16 x i8> @shuffle_v16i8_00_00_00_00_00_00_00_00_08_08_08_08_08_08_08_08(
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; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,8,8,8,8,8,8,8,8]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_00_00_00_00_00_00_00_00_08_08_08_08_08_08_08_08:
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; AVX: # BB#0:
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,8,8,8,8,8,8,8,8]
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; AVX-NEXT: retq
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; AVX1OR2-LABEL: shuffle_v16i8_00_00_00_00_00_00_00_00_08_08_08_08_08_08_08_08:
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; AVX1OR2: # BB#0:
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; AVX1OR2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,8,8,8,8,8,8,8,8]
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; AVX1OR2-NEXT: retq
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;
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; AVX512VL-LABEL: shuffle_v16i8_00_00_00_00_00_00_00_00_08_08_08_08_08_08_08_08:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,1,1,8,8,9,9,8,8,9,9,10,10,11,11]
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; AVX512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,2,2,4,5,6,7]
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
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; AVX512VL-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
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ret <16 x i8> %shuffle
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}
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@@ -184,10 +199,10 @@ define <16 x i8> @shuffle_v16i8_0101010101010101(<16 x i8> %a, <16 x i8> %b) {
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: shuffle_v16i8_0101010101010101:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
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; AVX2-NEXT: retq
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; AVX2OR512VL-LABEL: shuffle_v16i8_0101010101010101:
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; AVX2OR512VL: # BB#0:
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; AVX2OR512VL-NEXT: vpbroadcastw %xmm0, %xmm0
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; AVX2OR512VL-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
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ret <16 x i8> %shuffle
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}
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@@ -256,11 +271,11 @@ define <16 x i8> @shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07(
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; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1
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; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; AVX2-NEXT: retq
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; AVX2OR512VL-LABEL: shuffle_v16i8_16_00_16_01_16_02_16_03_16_04_16_05_16_06_16_07:
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; AVX2OR512VL: # BB#0:
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; AVX2OR512VL-NEXT: vpbroadcastb %xmm1, %xmm1
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; AVX2OR512VL-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; AVX2OR512VL-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 0, i32 16, i32 1, i32 16, i32 2, i32 16, i32 3, i32 16, i32 4, i32 16, i32 5, i32 16, i32 6, i32 16, i32 7>
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ret <16 x i8> %shuffle
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}
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@@ -400,11 +415,17 @@ define <16 x i8> @shuffle_v16i8_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31(
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; SSE41-NEXT: movdqa %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31:
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; AVX: # BB#0:
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
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; AVX-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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; AVX1OR2-LABEL: shuffle_v16i8_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31:
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; AVX1OR2: # BB#0:
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; AVX1OR2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
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; AVX1OR2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
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; AVX1OR2-NEXT: retq
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;
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; AVX512VL-LABEL: shuffle_v16i8_00_17_02_19_04_21_06_23_08_25_10_27_12_29_14_31:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vmovdqu8 {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
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; AVX512VL-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
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; AVX512VL-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
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ret <16 x i8> %shuffle
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}
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@@ -433,11 +454,17 @@ define <16 x i8> @shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31(
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; SSE41-NEXT: movdqa %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31:
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; AVX: # BB#0:
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,0,255,255,255,0,255,255,255,0,255,255,255,0]
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; AVX-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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; AVX1OR2-LABEL: shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31:
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; AVX1OR2: # BB#0:
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; AVX1OR2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,0,255,255,255,0,255,255,255,0,255,255,255,0]
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; AVX1OR2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
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; AVX1OR2-NEXT: retq
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;
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; AVX512VL-LABEL: shuffle_v16i8_00_01_02_19_04_05_06_23_08_09_10_27_12_13_14_31:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vmovdqu8 {{.*#+}} xmm2 = [255,255,255,0,255,255,255,0,255,255,255,0,255,255,255,0]
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; AVX512VL-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
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; AVX512VL-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 4, i32 5, i32 6, i32 23, i32 8, i32 9, i32 10, i32 27, i32 12, i32 13, i32 14, i32 31>
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ret <16 x i8> %shuffle
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}
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@@ -448,10 +475,15 @@ define <16 x i8> @shuffle_v16i8_00_01_02_zz_04_05_06_zz_08_09_10_zz_12_13_14_zz(
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_00_01_02_zz_04_05_06_zz_08_09_10_zz_12_13_14_zz:
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; AVX: # BB#0:
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; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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; AVX1OR2-LABEL: shuffle_v16i8_00_01_02_zz_04_05_06_zz_08_09_10_zz_12_13_14_zz:
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; AVX1OR2: # BB#0:
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; AVX1OR2-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX1OR2-NEXT: retq
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;
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; AVX512VL-LABEL: shuffle_v16i8_00_01_02_zz_04_05_06_zz_08_09_10_zz_12_13_14_zz:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vpandq {{.*}}(%rip), %xmm0, %xmm0
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; AVX512VL-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 4, i32 5, i32 6, i32 23, i32 8, i32 9, i32 10, i32 27, i32 12, i32 13, i32 14, i32 31>
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ret <16 x i8> %shuffle
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}
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@@ -480,11 +512,17 @@ define <16 x i8> @shuffle_v16i8_00_01_02_03_20_05_06_23_08_09_10_11_28_13_14_31(
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; SSE41-NEXT: movdqa %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_00_01_02_03_20_05_06_23_08_09_10_11_28_13_14_31:
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; AVX: # BB#0:
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,0,255,255,0,255,255,255,255,0,255,255,0]
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; AVX-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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; AVX1OR2-LABEL: shuffle_v16i8_00_01_02_03_20_05_06_23_08_09_10_11_28_13_14_31:
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; AVX1OR2: # BB#0:
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; AVX1OR2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,0,255,255,0,255,255,255,255,0,255,255,0]
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; AVX1OR2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
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; AVX1OR2-NEXT: retq
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;
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; AVX512VL-LABEL: shuffle_v16i8_00_01_02_03_20_05_06_23_08_09_10_11_28_13_14_31:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vmovdqu8 {{.*#+}} xmm2 = [255,255,255,255,0,255,255,0,255,255,255,255,0,255,255,0]
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; AVX512VL-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
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; AVX512VL-NEXT: retq
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%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 23, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 31>
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ret <16 x i8> %shuffle
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}
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@@ -514,11 +552,17 @@ define <16 x i8> @shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15(
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15:
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; AVX: # BB#0:
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,0,0,0,0,255,255,0,0,255,0,255,0]
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; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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; AVX1OR2-LABEL: shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15:
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; AVX1OR2: # BB#0:
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; AVX1OR2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,0,0,0,0,255,255,0,0,255,0,255,0]
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; AVX1OR2-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
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; AVX1OR2-NEXT: retq
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;
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; AVX512VL-LABEL: shuffle_v16i8_16_17_18_19_04_05_06_07_24_25_10_11_28_13_30_15:
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; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vmovdqu8 {{.*#+}} xmm2 = [255,255,255,255,0,0,0,0,255,255,0,0,255,0,255,0]
|
||||
; AVX512VL-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 10, i32 11, i32 28, i32 13, i32 30, i32 15>
|
||||
ret <16 x i8> %shuffle
|
||||
}
|
||||
@@ -658,11 +702,17 @@ define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(
|
||||
; SSE41-NEXT: pinsrb $5, %edi, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrb $5, %edi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: vpinsrb $5, %edi, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm0, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpinsrb $5, %edi, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%a = insertelement <16 x i8> undef, i8 %i, i32 0
|
||||
%shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
||||
ret <16 x i8> %shuffle
|
||||
@@ -689,11 +739,17 @@ define <16 x i8> @shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16(
|
||||
; SSE41-NEXT: pinsrb $15, %edi, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrb $15, %edi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: vpinsrb $15, %edi, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v16i8_zz_uu_uu_zz_uu_uu_zz_zz_zz_zz_zz_zz_zz_zz_zz_16:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm0, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpinsrb $15, %edi, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%a = insertelement <16 x i8> undef, i8 %i, i32 0
|
||||
%shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 16>
|
||||
ret <16 x i8> %shuffle
|
||||
@@ -720,11 +776,17 @@ define <16 x i8> @shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz(
|
||||
; SSE41-NEXT: pinsrb $2, %edi, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrb $2, %edi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: vpinsrb $2, %edi, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v16i8_zz_zz_19_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm0, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpinsrb $2, %edi, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%a = insertelement <16 x i8> undef, i8 %i, i32 3
|
||||
%shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 19, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
ret <16 x i8> %shuffle
|
||||
@@ -1124,12 +1186,19 @@ define <16 x i8> @shuffle_v16i8_uu_10_02_07_22_14_07_02_18_03_01_14_18_09_11_00(
|
||||
; SSE41-NEXT: por %xmm1, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v16i8_uu_10_02_07_22_14_07_02_18_03_01_14_18_09_11_00:
|
||||
; AVX: # BB#0: # %entry
|
||||
; AVX-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[2],zero,zero,zero
|
||||
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,10,2,7],zero,xmm0[14,7,2],zero,xmm0[3,1,14],zero,xmm0[9,11,0]
|
||||
; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v16i8_uu_10_02_07_22_14_07_02_18_03_01_14_18_09_11_00:
|
||||
; AVX1OR2: # BB#0: # %entry
|
||||
; AVX1OR2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[2],zero,zero,zero
|
||||
; AVX1OR2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,10,2,7],zero,xmm0[14,7,2],zero,xmm0[3,1,14],zero,xmm0[9,11,0]
|
||||
; AVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v16i8_uu_10_02_07_22_14_07_02_18_03_01_14_18_09_11_00:
|
||||
; AVX512VL: # BB#0: # %entry
|
||||
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[2],zero,zero,zero
|
||||
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,10,2,7],zero,xmm0[14,7,2],zero,xmm0[3,1,14],zero,xmm0[9,11,0]
|
||||
; AVX512VL-NEXT: vporq %xmm1, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
entry:
|
||||
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 undef, i32 10, i32 2, i32 7, i32 22, i32 14, i32 7, i32 2, i32 18, i32 3, i32 1, i32 14, i32 18, i32 9, i32 11, i32 0>
|
||||
|
||||
@@ -1156,12 +1225,19 @@ define void @constant_gets_selected(<4 x i32>* %ptr1, <4 x i32>* %ptr2) {
|
||||
; SSE-NEXT: movaps %xmm0, (%rsi)
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: constant_gets_selected:
|
||||
; AVX: # BB#0: # %entry
|
||||
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
|
||||
; AVX-NEXT: vmovaps %xmm0, (%rdi)
|
||||
; AVX-NEXT: vmovaps %xmm0, (%rsi)
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: constant_gets_selected:
|
||||
; AVX1OR2: # BB#0: # %entry
|
||||
; AVX1OR2-NEXT: vxorps %xmm0, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: vmovaps %xmm0, (%rdi)
|
||||
; AVX1OR2-NEXT: vmovaps %xmm0, (%rsi)
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: constant_gets_selected:
|
||||
; AVX512VL: # BB#0: # %entry
|
||||
; AVX512VL-NEXT: vpxord %xmm0, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vmovdqa32 %xmm0, (%rdi)
|
||||
; AVX512VL-NEXT: vmovdqa32 %xmm0, (%rsi)
|
||||
; AVX512VL-NEXT: retq
|
||||
entry:
|
||||
%weird_zero = bitcast <4 x i32> zeroinitializer to <16 x i8>
|
||||
%shuffle.i = shufflevector <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %weird_zero, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
|
||||
@@ -1298,13 +1374,21 @@ define <16 x i8> @PR12412(<16 x i8> %inval1, <16 x i8> %inval2) {
|
||||
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: PR12412:
|
||||
; AVX: # BB#0: # %entry
|
||||
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
|
||||
; AVX-NEXT: vpshufb %xmm2, %xmm1, %xmm1
|
||||
; AVX-NEXT: vpshufb %xmm2, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: PR12412:
|
||||
; AVX1OR2: # BB#0: # %entry
|
||||
; AVX1OR2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
|
||||
; AVX1OR2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
|
||||
; AVX1OR2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: PR12412:
|
||||
; AVX512VL: # BB#0: # %entry
|
||||
; AVX512VL-NEXT: vmovdqu8 {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
|
||||
; AVX512VL-NEXT: vpshufb %xmm2, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpshufb %xmm2, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX512VL-NEXT: retq
|
||||
entry:
|
||||
%0 = shufflevector <16 x i8> %inval1, <16 x i8> %inval2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
|
||||
ret <16 x i8> %0
|
||||
@@ -1373,10 +1457,10 @@ define <16 x i8> @insert_dup_mem_v16i8_i32(i32* %ptr) {
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_dup_mem_v16i8_i32:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastb (%rdi), %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: insert_dup_mem_v16i8_i32:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastb (%rdi), %xmm0
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%tmp = load i32, i32* %ptr, align 4
|
||||
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %tmp, i32 0
|
||||
%tmp2 = bitcast <4 x i32> %tmp1 to <16 x i8>
|
||||
@@ -1418,10 +1502,10 @@ define <16 x i8> @insert_dup_mem_v16i8_sext_i8(i8* %ptr) {
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_dup_mem_v16i8_sext_i8:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastb (%rdi), %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: insert_dup_mem_v16i8_sext_i8:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastb (%rdi), %xmm0
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%tmp = load i8, i8* %ptr, align 1
|
||||
%tmp1 = sext i8 %tmp to i32
|
||||
%tmp2 = insertelement <4 x i32> zeroinitializer, i32 %tmp1, i32 0
|
||||
@@ -1457,10 +1541,10 @@ define <16 x i8> @insert_dup_elt1_mem_v16i8_i32(i32* %ptr) {
|
||||
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_dup_elt1_mem_v16i8_i32:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastb 1(%rdi), %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: insert_dup_elt1_mem_v16i8_i32:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastb 1(%rdi), %xmm0
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%tmp = load i32, i32* %ptr, align 4
|
||||
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %tmp, i32 0
|
||||
%tmp2 = bitcast <4 x i32> %tmp1 to <16 x i8>
|
||||
@@ -1495,10 +1579,10 @@ define <16 x i8> @insert_dup_elt2_mem_v16i8_i32(i32* %ptr) {
|
||||
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_dup_elt2_mem_v16i8_i32:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastb 2(%rdi), %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: insert_dup_elt2_mem_v16i8_i32:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastb 2(%rdi), %xmm0
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%tmp = load i32, i32* %ptr, align 4
|
||||
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %tmp, i32 0
|
||||
%tmp2 = bitcast <4 x i32> %tmp1 to <16 x i8>
|
||||
@@ -1544,6 +1628,13 @@ define <16 x i8> @insert_dup_elt1_mem_v16i8_sext_i8(i8* %ptr) {
|
||||
; AVX2-NEXT: vmovd %eax, %xmm0
|
||||
; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: insert_dup_elt1_mem_v16i8_sext_i8:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: movsbl (%rdi), %eax
|
||||
; AVX512VL-NEXT: shrl $8, %eax
|
||||
; AVX512VL-NEXT: vpbroadcastb %al, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%tmp = load i8, i8* %ptr, align 1
|
||||
%tmp1 = sext i8 %tmp to i32
|
||||
%tmp2 = insertelement <4 x i32> zeroinitializer, i32 %tmp1, i32 0
|
||||
@@ -1590,6 +1681,13 @@ define <16 x i8> @insert_dup_elt2_mem_v16i8_sext_i8(i8* %ptr) {
|
||||
; AVX2-NEXT: vmovd %eax, %xmm0
|
||||
; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: insert_dup_elt2_mem_v16i8_sext_i8:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: movsbl (%rdi), %eax
|
||||
; AVX512VL-NEXT: shrl $16, %eax
|
||||
; AVX512VL-NEXT: vpbroadcastb %al, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%tmp = load i8, i8* %ptr, align 1
|
||||
%tmp1 = sext i8 %tmp to i32
|
||||
%tmp2 = insertelement <4 x i32> zeroinitializer, i32 %tmp1, i32 0
|
||||
|
||||
@@ -3,8 +3,9 @@
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1OR2 --check-prefix=AVX1
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1OR2 --check-prefix=AVX2OR512VL --check-prefix=AVX2
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx512vl,+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2OR512VL --check-prefix=AVX512VL
|
||||
|
||||
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
||||
target triple = "x86_64-unknown-unknown"
|
||||
@@ -361,11 +362,11 @@ define <4 x i32> @shuffle_v4i32_0124(<4 x i32> %a, <4 x i32> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v4i32_0124:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastd %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v4i32_0124:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastd %xmm1, %xmm1
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -402,12 +403,12 @@ define <4 x i32> @shuffle_v4i32_0142(<4 x i32> %a, <4 x i32> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v4i32_0142:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastq %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v4i32_0142:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastq %xmm1, %xmm1
|
||||
; AVX2OR512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -447,12 +448,12 @@ define <4 x i32> @shuffle_v4i32_0412(<4 x i32> %a, <4 x i32> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v4i32_0412:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastd %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,2]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v4i32_0412:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastd %xmm1, %xmm1
|
||||
; AVX2OR512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,2]
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 2>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -490,11 +491,11 @@ define <4 x i32> @shuffle_v4i32_4012(<4 x i32> %a, <4 x i32> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v4i32_4012:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,2]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v4i32_4012:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,2]
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -544,12 +545,12 @@ define <4 x i32> @shuffle_v4i32_0451(<4 x i32> %a, <4 x i32> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v4i32_0451:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
|
||||
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v4i32_0451:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
|
||||
; AVX2OR512VL-NEXT: vpbroadcastq %xmm0, %xmm0
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 1>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -600,12 +601,12 @@ define <4 x i32> @shuffle_v4i32_4015(<4 x i32> %a, <4 x i32> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v4i32_4015:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastq %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v4i32_4015:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastq %xmm1, %xmm1
|
||||
; AVX2OR512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 5>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -638,11 +639,17 @@ define <4 x float> @shuffle_v4f32_4zzz(<4 x float> %a) {
|
||||
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v4f32_4zzz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v4f32_4zzz:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX1OR2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v4f32_4zzz:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
|
||||
ret <4 x float> %shuffle
|
||||
}
|
||||
@@ -1190,11 +1197,17 @@ define <4 x i32> @shuffle_v4i32_4zzz(<4 x i32> %a) {
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v4i32_4zzz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v4i32_4zzz:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1OR2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v4i32_4zzz:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -1228,12 +1241,19 @@ define <4 x i32> @shuffle_v4i32_z4zz(<4 x i32> %a) {
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,0,1,1]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v4i32_z4zz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v4i32_z4zz:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1OR2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
||||
; AVX1OR2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v4i32_z4zz:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -1267,12 +1287,19 @@ define <4 x i32> @shuffle_v4i32_zz4z(<4 x i32> %a) {
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,1]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v4i32_zz4z:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,0,1]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v4i32_zz4z:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1OR2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
||||
; AVX1OR2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,0,1]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v4i32_zz4z:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,0,1]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 4, i32 0>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -1333,6 +1360,13 @@ define <4 x i32> @shuffle_v4i32_z6zz(<4 x i32> %a) {
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v4i32_z6zz:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -1654,6 +1688,12 @@ define <4 x i32> @shuffle_v4i32_0z23(<4 x i32> %a) {
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v4i32_0z23:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -1691,6 +1731,12 @@ define <4 x i32> @shuffle_v4i32_01z3(<4 x i32> %a) {
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v4i32_01z3:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -1728,6 +1774,12 @@ define <4 x i32> @shuffle_v4i32_012z(<4 x i32> %a) {
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v4i32_012z:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -1765,6 +1817,12 @@ define <4 x i32> @shuffle_v4i32_0zz3(<4 x i32> %a) {
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v4i32_0zz3:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 3>
|
||||
ret <4 x i32> %shuffle
|
||||
}
|
||||
@@ -1935,10 +1993,10 @@ define <4 x i32> @mask_v4i32_0127(<4 x i32> %a, <4 x i32> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: mask_v4i32_0127:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: mask_v4i32_0127:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%1 = bitcast <4 x i32> %a to <2 x i64>
|
||||
%2 = bitcast <4 x i32> %b to <2 x i64>
|
||||
%3 = and <2 x i64> %1, <i64 0, i64 -4294967296>
|
||||
@@ -2095,11 +2153,11 @@ define <4 x i32> @insert_reg_lo_v4i32(i64 %a, <4 x i32> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_reg_lo_v4i32:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vmovq %rdi, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: insert_reg_lo_v4i32:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vmovq %rdi, %xmm1
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%a.cast = bitcast i64 %a to <2 x i32>
|
||||
%v = shufflevector <2 x i32> %a.cast, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
||||
%shuffle = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
|
||||
@@ -2139,6 +2197,13 @@ define <4 x i32> @insert_mem_lo_v4i32(<2 x i32>* %ptr, <4 x i32> %b) {
|
||||
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: insert_mem_lo_v4i32:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
|
||||
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%a = load <2 x i32>, <2 x i32>* %ptr
|
||||
%v = shufflevector <2 x i32> %a, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
||||
%shuffle = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
|
||||
@@ -2170,11 +2235,18 @@ define <4 x i32> @insert_mem_hi_v4i32(<2 x i32>* %ptr, <4 x i32> %b) {
|
||||
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: insert_mem_hi_v4i32:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
|
||||
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: insert_mem_hi_v4i32:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
|
||||
; AVX1OR2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: insert_mem_hi_v4i32:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
|
||||
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%a = load <2 x i32>, <2 x i32>* %ptr
|
||||
%v = shufflevector <2 x i32> %a, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
||||
%shuffle = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
|
||||
|
||||
@@ -2,8 +2,9 @@
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1OR2 --check-prefix=AVX1
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1OR2 --check-prefix=AVX2OR512VL --check-prefix=AVX2
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx512vl,+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2OR512VL --check-prefix=AVX512VL
|
||||
|
||||
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
||||
target triple = "x86_64-unknown-unknown"
|
||||
@@ -73,10 +74,10 @@ define <8 x i16> @shuffle_v8i16_00000000(<8 x i16> %a, <8 x i16> %b) {
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v8i16_00000000:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v8i16_00000000:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastw %xmm0, %xmm0
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -702,10 +703,17 @@ define <8 x i16> @shuffle_v8i16_0127XXXX(<8 x i16> %a, <8 x i16> %b) {
|
||||
; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,14,15,4,5,14,15,12,13,14,15]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_0127XXXX:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,14,15,4,5,14,15,12,13,14,15]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_0127XXXX:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,14,15,4,5,14,15,12,13,14,15]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_0127XXXX:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; AVX512VL-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,7,6,7]
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -728,10 +736,17 @@ define <8 x i16> @shuffle_v8i16_XXXX4563(<8 x i16> %a, <8 x i16> %b) {
|
||||
; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[12,13,6,7,4,5,6,7,8,9,10,11,12,13,6,7]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_XXXX4563:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[12,13,6,7,4,5,6,7,8,9,10,11,12,13,6,7]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_XXXX4563:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[12,13,6,7,4,5,6,7,8,9,10,11,12,13,6,7]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_XXXX4563:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
|
||||
; AVX512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,3,2,3,4,5,6,7]
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,0]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 4, i32 5, i32 6, i32 3>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -754,10 +769,17 @@ define <8 x i16> @shuffle_v8i16_4563XXXX(<8 x i16> %a, <8 x i16> %b) {
|
||||
; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,6,7,8,9,10,11,0,1,2,3]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_4563XXXX:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,6,7,8,9,10,11,0,1,2,3]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_4563XXXX:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,6,7,8,9,10,11,0,1,2,3]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_4563XXXX:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
|
||||
; AVX512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,3,2,3,4,5,6,7]
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -780,10 +802,17 @@ define <8 x i16> @shuffle_v8i16_01274563(<8 x i16> %a, <8 x i16> %b) {
|
||||
; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,14,15,8,9,10,11,12,13,6,7]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_01274563:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,14,15,8,9,10,11,12,13,6,7]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_01274563:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,14,15,8,9,10,11,12,13,6,7]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_01274563:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; AVX512VL-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,4,7]
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,3,1,2]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 3>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -806,10 +835,17 @@ define <8 x i16> @shuffle_v8i16_45630127(<8 x i16> %a, <8 x i16> %b) {
|
||||
; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,6,7,0,1,2,3,4,5,14,15]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_45630127:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,6,7,0,1,2,3,4,5,14,15]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_45630127:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,6,7,0,1,2,3,4,5,14,15]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_45630127:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
|
||||
; AVX512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,3,2,1,4,5,6,7]
|
||||
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,3,1]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 3, i32 0, i32 1, i32 2, i32 7>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -1070,11 +1106,11 @@ define <8 x i16> @shuffle_v8i16_032dXXXX(<8 x i16> %a, <8 x i16> %b) {
|
||||
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,6,7,4,5,10,11,0,1,10,11,0,1,2,3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v8i16_032dXXXX:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
||||
; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,6,7,4,5,10,11,0,1,10,11,0,1,2,3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v8i16_032dXXXX:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
||||
; AVX2OR512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,6,7,4,5,10,11,0,1,10,11,0,1,2,3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 3, i32 2, i32 13, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -1154,11 +1190,11 @@ define <8 x i16> @shuffle_v8i16_XXXXcde3(<8 x i16> %a, <8 x i16> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5,6],xmm0[7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v8i16_XXXXcde3:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5,6],xmm0[7]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v8i16_XXXXcde3:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastq %xmm0, %xmm0
|
||||
; AVX2OR512VL-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5,6],xmm0[7]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 3>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -1228,11 +1264,11 @@ define <8 x i16> @shuffle_v8i16_012dcde3(<8 x i16> %a, <8 x i16> %b) {
|
||||
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v8i16_012dcde3:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
||||
; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v8i16_012dcde3:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
||||
; AVX2OR512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 12, i32 13, i32 14, i32 3>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -1303,13 +1339,13 @@ define <8 x i16> @shuffle_v8i16_XXX1X579(<8 x i16> %a, <8 x i16> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v8i16_XXX1X579:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastd %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
|
||||
; AVX2-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7]
|
||||
; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v8i16_XXX1X579:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastd %xmm1, %xmm1
|
||||
; AVX2OR512VL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
|
||||
; AVX2OR512VL-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7]
|
||||
; AVX2OR512VL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 5, i32 7, i32 9>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -1345,12 +1381,12 @@ define <8 x i16> @shuffle_v8i16_XX4X8acX(<8 x i16> %a, <8 x i16> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: shuffle_v8i16_XX4X8acX:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5]
|
||||
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: shuffle_v8i16_XX4X8acX:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5]
|
||||
; AVX2OR512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 undef, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 undef>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -1379,11 +1415,17 @@ define <8 x i16> @shuffle_v8i16_z8zzzzzz(i16 %i) {
|
||||
; SSE-NEXT: pinsrw $1, %edi, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_z8zzzzzz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_z8zzzzzz:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_z8zzzzzz:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm0, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%a = insertelement <8 x i16> undef, i16 %i, i32 0
|
||||
%shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 2, i32 8, i32 3, i32 7, i32 6, i32 5, i32 4, i32 3>
|
||||
ret <8 x i16> %shuffle
|
||||
@@ -1396,11 +1438,17 @@ define <8 x i16> @shuffle_v8i16_zzzzz8zz(i16 %i) {
|
||||
; SSE-NEXT: pinsrw $5, %edi, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_zzzzz8zz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_zzzzz8zz:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_zzzzz8zz:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm0, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%a = insertelement <8 x i16> undef, i16 %i, i32 0
|
||||
%shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 8, i32 0, i32 0>
|
||||
ret <8 x i16> %shuffle
|
||||
@@ -1413,11 +1461,17 @@ define <8 x i16> @shuffle_v8i16_zuuzuuz8(i16 %i) {
|
||||
; SSE-NEXT: pinsrw $7, %edi, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_zuuzuuz8:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_zuuzuuz8:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_zuuzuuz8:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm0, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%a = insertelement <8 x i16> undef, i16 %i, i32 0
|
||||
%shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 0, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 6, i32 8>
|
||||
ret <8 x i16> %shuffle
|
||||
@@ -1430,11 +1484,17 @@ define <8 x i16> @shuffle_v8i16_zzBzzzzz(i16 %i) {
|
||||
; SSE-NEXT: pinsrw $2, %edi, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_zzBzzzzz:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $2, %edi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_zzBzzzzz:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: vpinsrw $2, %edi, %xmm0, %xmm0
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_zzBzzzzz:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm0, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpinsrw $2, %edi, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%a = insertelement <8 x i16> undef, i16 %i, i32 3
|
||||
%shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 11, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i16> %shuffle
|
||||
@@ -2042,11 +2102,17 @@ define <8 x i16> @shuffle_v8i16_0z234567(<8 x i16> %a) {
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_0z234567:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_0z234567:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1OR2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_0z234567:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -2068,11 +2134,17 @@ define <8 x i16> @shuffle_v8i16_0zzzz5z7(<8 x i16> %a) {
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4],xmm0[5],xmm1[6],xmm0[7]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_0zzzz5z7:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4],xmm0[5],xmm1[6],xmm0[7]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_0zzzz5z7:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1OR2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4],xmm0[5],xmm1[6],xmm0[7]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_0zzzz5z7:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4],xmm0[5],xmm1[6],xmm0[7]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 8, i32 8, i32 8, i32 5, i32 8, i32 7>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -2094,11 +2166,17 @@ define <8 x i16> @shuffle_v8i16_0123456z(<8 x i16> %a) {
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6],xmm1[7]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: shuffle_v8i16_0123456z:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6],xmm1[7]
|
||||
; AVX-NEXT: retq
|
||||
; AVX1OR2-LABEL: shuffle_v8i16_0123456z:
|
||||
; AVX1OR2: # BB#0:
|
||||
; AVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX1OR2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6],xmm1[7]
|
||||
; AVX1OR2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: shuffle_v8i16_0123456z:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6],xmm1[7]
|
||||
; AVX512VL-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
|
||||
ret <8 x i16> %shuffle
|
||||
}
|
||||
@@ -2162,10 +2240,10 @@ define <8 x i16> @mask_v8i16_012345ef(<8 x i16> %a, <8 x i16> %b) {
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: mask_v8i16_012345ef:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: mask_v8i16_012345ef:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%1 = bitcast <8 x i16> %a to <2 x i64>
|
||||
%2 = bitcast <8 x i16> %b to <2 x i64>
|
||||
%3 = and <2 x i64> %1, <i64 0, i64 -4294967296>
|
||||
@@ -2190,10 +2268,10 @@ define <8 x i16> @insert_dup_mem_v8i16_i32(i32* %ptr) {
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_dup_mem_v8i16_i32:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastw (%rdi), %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: insert_dup_mem_v8i16_i32:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastw (%rdi), %xmm0
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%tmp = load i32, i32* %ptr, align 4
|
||||
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %tmp, i32 0
|
||||
%tmp2 = bitcast <4 x i32> %tmp1 to <8 x i16>
|
||||
@@ -2237,6 +2315,12 @@ define <8 x i16> @insert_dup_mem_v8i16_sext_i16(i16* %ptr) {
|
||||
; AVX2-NEXT: vmovd %eax, %xmm0
|
||||
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: insert_dup_mem_v8i16_sext_i16:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: movswl (%rdi), %eax
|
||||
; AVX512VL-NEXT: vpbroadcastw %ax, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%tmp = load i16, i16* %ptr, align 2
|
||||
%tmp1 = sext i16 %tmp to i32
|
||||
%tmp2 = insertelement <4 x i32> zeroinitializer, i32 %tmp1, i32 0
|
||||
@@ -2260,10 +2344,10 @@ define <8 x i16> @insert_dup_elt1_mem_v8i16_i32(i32* %ptr) {
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_dup_elt1_mem_v8i16_i32:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastw 2(%rdi), %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: insert_dup_elt1_mem_v8i16_i32:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastw 2(%rdi), %xmm0
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%tmp = load i32, i32* %ptr, align 4
|
||||
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %tmp, i32 0
|
||||
%tmp2 = bitcast <4 x i32> %tmp1 to <8 x i16>
|
||||
@@ -2298,10 +2382,10 @@ define <8 x i16> @insert_dup_elt3_mem_v8i16_i32(i32* %ptr) {
|
||||
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_dup_elt3_mem_v8i16_i32:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpbroadcastw 2(%rdi), %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
; AVX2OR512VL-LABEL: insert_dup_elt3_mem_v8i16_i32:
|
||||
; AVX2OR512VL: # BB#0:
|
||||
; AVX2OR512VL-NEXT: vpbroadcastw 2(%rdi), %xmm0
|
||||
; AVX2OR512VL-NEXT: retq
|
||||
%tmp = load i32, i32* %ptr, align 4
|
||||
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %tmp, i32 1
|
||||
%tmp2 = bitcast <4 x i32> %tmp1 to <8 x i16>
|
||||
@@ -2346,6 +2430,13 @@ define <8 x i16> @insert_dup_elt1_mem_v8i16_sext_i16(i16* %ptr) {
|
||||
; AVX2-NEXT: vmovd %eax, %xmm0
|
||||
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: insert_dup_elt1_mem_v8i16_sext_i16:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: movswl (%rdi), %eax
|
||||
; AVX512VL-NEXT: shrl $16, %eax
|
||||
; AVX512VL-NEXT: vpbroadcastw %ax, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%tmp = load i16, i16* %ptr, align 2
|
||||
%tmp1 = sext i16 %tmp to i32
|
||||
%tmp2 = insertelement <4 x i32> zeroinitializer, i32 %tmp1, i32 0
|
||||
@@ -2392,6 +2483,13 @@ define <8 x i16> @insert_dup_elt3_mem_v8i16_sext_i16(i16* %ptr) {
|
||||
; AVX2-NEXT: vmovd %eax, %xmm0
|
||||
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: insert_dup_elt3_mem_v8i16_sext_i16:
|
||||
; AVX512VL: # BB#0:
|
||||
; AVX512VL-NEXT: movswl (%rdi), %eax
|
||||
; AVX512VL-NEXT: shrl $16, %eax
|
||||
; AVX512VL-NEXT: vpbroadcastw %ax, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
%tmp = load i16, i16* %ptr, align 2
|
||||
%tmp1 = sext i16 %tmp to i32
|
||||
%tmp2 = insertelement <4 x i32> zeroinitializer, i32 %tmp1, i32 1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user