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[DAGCombiner] add operation legality checks before creating shift ops (PR43542)

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As discussed on llvm-dev and:
https://bugs.llvm.org/show_bug.cgi?id=43542
...we have transforms that assume shift operations are legal and transforms to
use them are profitable, but that may not hold for simple targets.

In this case, the MSP430 target custom lowers shifts by repeating (many)
simpler/fixed ops. That can be avoided by keeping this code as setcc/select.

Differential Revision: https://reviews.llvm.org/D68397

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373666 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel
2019-10-03 21:34:04 +00:00
parent 091533bd66
commit f03d2d8516
2 changed files with 29 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+6 -1
View File
@@ -19911,8 +19911,13 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
// when the condition can be materialized as an all-ones register. Any
// single bit-test can be materialized as an all-ones register with
// shift-left and shift-right-arith.
// TODO: The operation legality checks could be loosened to include "custom",
// but that may cause regressions for targets that do not have shift
// instructions.
if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2) &&
TLI.isOperationLegal(ISD::SHL, VT) &&
TLI.isOperationLegal(ISD::SRA, VT)) {
SDValue AndLHS = N0->getOperand(0);
auto *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
test/CodeGen/MSP430/selectcc.ll
+23 -38
View File
@@ -4,24 +4,13 @@
define i16 @select_to_shifts_i16(i16 %a, i16 %b) {
; CHECK-LABEL: select_to_shifts_i16:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov.b r12, r12
; CHECK-NEXT: swpb r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: swpb r12
; CHECK-NEXT: sxt r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: and r13, r12
; CHECK-NEXT: mov r12, r14
; CHECK-NEXT: clr r12
; CHECK-NEXT: bit #2, r14
; CHECK-NEXT: jeq .LBB0_2
; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: mov r13, r12
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ret
%and = and i16 %a, 2
%tobool = icmp eq i16 %and, 0
@@ -32,27 +21,23 @@ define i16 @select_to_shifts_i16(i16 %a, i16 %b) {
define i32 @select_to_shifts_i32(i32 %a, i32 %b) {
; CHECK-LABEL: select_to_shifts_i32:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov r12, r13
; CHECK-NEXT: mov.b r13, r13
; CHECK-NEXT: swpb r13
; CHECK-NEXT: add r13, r13
; CHECK-NEXT: add r13, r13
; CHECK-NEXT: add r13, r13
; CHECK-NEXT: add r13, r13
; CHECK-NEXT: add r13, r13
; CHECK-NEXT: add r13, r13
; CHECK-NEXT: swpb r13
; CHECK-NEXT: sxt r13
; CHECK-NEXT: rra r13
; CHECK-NEXT: rra r13
; CHECK-NEXT: rra r13
; CHECK-NEXT: rra r13
; CHECK-NEXT: rra r13
; CHECK-NEXT: rra r13
; CHECK-NEXT: rra r13
; CHECK-NEXT: and r13, r14
; CHECK-NEXT: and r15, r13
; CHECK-NEXT: mov r12, r11
; CHECK-NEXT: and #2, r11
; CHECK-NEXT: clr r13
; CHECK-NEXT: tst r11
; CHECK-NEXT: clr r12
; CHECK-NEXT: jne .LBB1_3
; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: tst r11
; CHECK-NEXT: jne .LBB1_4
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: mov r14, r12
; CHECK-NEXT: tst r11
; CHECK-NEXT: jeq .LBB1_2
; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: mov r15, r13
; CHECK-NEXT: ret
%and = and i32 %a, 2
%tobool = icmp eq i32 %and, 0