RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2026-07-01 21:04:04 -04:00
Code Issues Packages Projects Releases 10 Wiki Activity

[GISel][CallLowering] Enable vector support in argument lowering

Browse Source 
The exciting code is actually already enough to handle the splitting
of vector arguments but we were lacking a test case.

This commit adds a test case for vector argument lowering involving
splitting and enable the related support in call lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374589 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet
2019-10-11 20:22:57 +00:00
parent 094c72f8b4
commit f4daa70c54
2 changed files with 24 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CodeGen/GlobalISel/CallLowering.cpp
+2 -4
View File
@@ -198,14 +198,12 @@ bool CallLowering::handleAssignments(CCState &CCInfo,
unsigned NumParts = TLI->getNumRegistersForCallingConv(
F.getContext(), F.getCallingConv(), CurVT);
if (NumParts > 1) {
if (CurVT.isVector())
return false;
// For now only handle exact splits.
if (NewVT.getSizeInBits() * NumParts != CurVT.getSizeInBits())
return false;
}
// For incoming arguments (return values), we could have values in
// For incoming arguments (physregs to vregs), we could have values in
// physregs (or memlocs) which we want to extract and copy to vregs.
// During this, we might have to deal with the LLT being split across
// multiple regs, so we have to record this information for later.
@@ -221,7 +219,7 @@ bool CallLowering::handleAssignments(CCState &CCInfo,
return false;
} else {
// We're handling an incoming arg which is split over multiple regs.
// E.g. returning an s128 on AArch64.
// E.g. passing an s128 on AArch64.
ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
Args[i].OrigRegs.push_back(Args[i].Regs[0]);
Args[i].Regs.clear();
test/CodeGen/AArch64/GlobalISel/irtranslator-split-vector-arg.ll
+22
View File
@@ -0,0 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -global-isel-abort=1 %s -stop-after=irtranslator -o - | FileCheck %s
target triple = "aarch64-apple-ios"
; Check that we correctly split %arg into two vector registers of
; size <2 x i64>.
define hidden fastcc <4 x float> @foo(<4 x i64> %arg) unnamed_addr #0 {
; CHECK-LABEL: name: foo
; CHECK: bb.1.bb:
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)
; CHECK: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP [[CONCAT_VECTORS]](<4 x s64>)
; CHECK: $q0 = COPY [[UITOFP]](<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
bb:
%tmp = uitofp <4 x i64> %arg to <4 x float>
ret <4 x float> %tmp
}
attributes #0 = { nounwind readnone }