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GlobalISel: partially revert r308540.

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An unfinished and untested implementation of ISel for G_UNMERGE_VALUES crept in
by mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308542 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2017-07-19 22:11:08 +00:00
parent a575cf69b3
commit f54b9c71c7
1 changed files with 0 additions and 24 deletions
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24
lib/Target/AArch64/AArch64InstructionSelector.cpp
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@ -780,30 +780,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
case TargetOpcode::G_UNMERGE_VALUES: {
//
LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
// Larger extracts are vectors, same-size extracts should be something else
// by now (either split up or simplified to a COPY).
if (SrcTy.getSizeInBits() > 64 || Ty.getSizeInBits() > 32)
return false;
I.setDesc(TII.get(AArch64::UBFMXri));
MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() +
Ty.getSizeInBits() - 1);
unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),
TII.get(AArch64::COPY))
.addDef(I.getOperand(0).getReg())
.addUse(DstReg, 0, AArch64::sub_32);
RBI.constrainGenericRegister(I.getOperand(0).getReg(),
AArch64::GPR32RegClass, MRI);
I.getOperand(0).setReg(DstReg);
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
case TargetOpcode::G_INSERT: {
LLT SrcTy = MRI.getType(I.getOperand(2).getReg());
// Larger inserts are vectors, same-size ones should be something else by