2 Commits

Author SHA1 Message Date
Matt Arsenault 7341697872 AMDGPU: Introduce a flag to disable mul24 intrinsic formation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369856 91177308-0d34-0410-b5e6-96231b3b80d8
2019-08-24 22:14:41 +00:00
Matt Arsenault b508009134 AMDGPU: Add 24-bit mul intrinsics
Insert these during codegenprepare.

This works around a DAG issue where generic combines eliminate the and
asserting the high bits are zero, which then exposes an unknown read
source to the mul combine. It doesn't worth the hassle of trying to
insert an AssertZext or something to try to deal with it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366094 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-15 17:50:31 +00:00