13 Commits

Author SHA1 Message Date
Matt Arsenault 389d538ccc AMDGPU: Look through bundles for existing waitcnts
These aren't produced now, but will be in a future patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364983 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-03 00:30:44 +00:00
Matt Arsenault 344372bde7 AMDGPU: Fix broken test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364935 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-02 15:34:40 +00:00
Stanislav Mekhanoshin 0b378026ac [AMDGPU] gfx1010 VMEM and SMEM implementation
Differential Revision: https://reviews.llvm.org/D61330

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359621 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-30 22:08:23 +00:00
David Stuttard 4b43b47d8a [AMDGPU] Add support for immediate operand for S_ENDPGM
Summary:
Add support for immediate operand in S_ENDPGM

Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6

Reviewers: alexshap

Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59213

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355902 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-12 09:52:58 +00:00
Mark Searles 8177aafa74 [AMDGPU][Waitcnt] Fix handling of flat instrs
On GFX9 and earlier, flat memory ops may decrement VMCNT out-of-order as well as LGKMCNT out-of-order.

Differential Revision: https://reviews.llvm.org/D46616

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333926 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-04 16:51:59 +00:00
Mark Searles ac95aa5361 [AMDGPU][Waitcnt] Remove the old waitcnt pass
Remove the old waitcnt pass ( si-insert-waits ), which is no longer maintained
and getting crufty

Differential Revision: https://reviews.llvm.org/D46448

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331641 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-07 14:43:28 +00:00
Yaxun Liu a2386c3b26 [AMDGPU] Switch to the new addr space mapping by default
This requires corresponding clang change.

Differential Revision: https://reviews.llvm.org/D40955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324101 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-02 16:07:16 +00:00
Puyan Lotfi 1076969bfe Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323922 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-31 22:04:26 +00:00
Matt Arsenault 4923776ab2 AMDGPU: Start adding offset fields to flat instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305194 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-12 15:55:58 +00:00
Matt Arsenault 9f4e5a06c6 AMDGPU: Remove tfe bit from flat instruction definitions
We don't use it and it was removed in gfx9, and the encoding
bit repurposed.

Additionally actually using it requires changing the output register
class, which wasn't done anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302814 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-11 17:38:33 +00:00
Matt Arsenault d706d030af AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
Currently the default C calling convention functions are treated
the same as compute kernels. Make this explicit so the default
calling convention can be changed to a non-kernel.

Converted with perl -pi -e 's/define void/define amdgpu_kernel void/'
on the relevant test directories (and undoing in one place that actually
wanted a non-kernel).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298444 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21 21:39:51 +00:00
Matt Arsenault f06f68a796 AMDGPU: Don't wait at end of block with a trivial successor
If there is only one successor, and that successor only
has one predecessor the wait can obviously be delayed until
uses or the end of the next block. This avoids code quality
regressions when there are trivial fallthrough blocks inserted
for structurization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297251 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-08 01:06:58 +00:00
Matthias Braun b321d17e29 Move .mir tests to appropriate directories
test/CodeGen/MIR should contain tests that intent to test the MIR
printing or parsing. Tests that test something else should be in
test/CodeGen/TargetName even when they are written in .mir.

As a rule of thumb, only tests using "llc -run-pass none" should be in
test/CodeGen/MIR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289254 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-09 19:08:15 +00:00