3 Commits

Author	SHA1	Message	Date
Sam Parker	6b90b027ec	[ARM][ParallelDSP] Change smlad insertion order ... Instead of inserting everything after the 'root' of the reduction, insert all instructions as close to their operands as possible. This can help reduce register pressure. Differential Revision: https://reviews.llvm.org/D67392 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374981 91177308-0d34-0410-b5e6-96231b3b80d8	2019-10-16 09:37:03 +00:00
David Green	63b13eaf70	[ARM] Cortex-M4 schedule additions ... This is an attempt to fill in some of the missing instructions from the Cortex-M4 schedule, and make it easier to do the same for other ARM cpus. - Some instructions are marked as hasNoSchedulingInfo as they are pseudos or otherwise do not require scheduling info - A lot of features have been marked not supported - Some WriteRes's have been added for cvt instructions. - Some extra instruction latencies have been added, notably by relaxing the regex for dsp instruction to catch more cases, and some fp instructions. This goes a long way to get the CompleteModel working for this CPU. It does not go far enough as to get all scheduling info for all output operands correct. Differential Revision: https://reviews.llvm.org/D67957 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373163 91177308-0d34-0410-b5e6-96231b3b80d8	2019-09-29 08:38:48 +00:00
Sam Parker	9ed919502b	[NFC][ARM] Add and modify tests ... Add test for ParallelDSP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371594 91177308-0d34-0410-b5e6-96231b3b80d8	2019-09-11 08:17:48 +00:00