13 Commits

Author SHA1 Message Date
Jinsong Ji f3b774599a [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC
All tests with -run-pass !=none should not in MIR/, See MIR/README.

```
Tests for codegen passes should NOT be here but in
test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.
```

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371857 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 14:18:36 +00:00
Kai Luo 7477c288b1 [PowerPC][MCP][NFC] Pre-commit test cases for https://reviews.llvm.org/D65267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371717 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-12 09:00:44 +00:00
Guillaume Chatelet 75f0bef615 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371608 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-11 11:16:48 +00:00
Kai Luo 122b03d246 [PowerPC][Peephole] Check if extsw's second operand is a virtual register
Summary:
When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check
if `extsw`'s second operand is a virtual register, otherwise we might
get miscompile.

Differential Revision: https://reviews.llvm.org/D65315

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367645 91177308-0d34-0410-b5e6-96231b3b80d8
2019-08-02 03:14:17 +00:00
Kai Luo 9eb46b73fc [PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli
Added a test case to show codegen differences.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366666 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-22 05:32:20 +00:00
Zaara Syeda 7bade9c965 [Power9] Allow gpr callee saved spills in prologue to vectors registers
Currently in llvm, CalleeSavedInfo can only assign a callee saved register to
stack frame index to be spilled in the prologue. We would like to enable
spilling gprs to vector registers. This patch adds the capability to spill to
other registers aside from just the stack. It also adds the changes for power9
to spill gprs to volatile vector registers when they are available.
This happens only for leaf functions when using the option
-ppc-enable-pe-vector-spills.

Differential Revision: https://reviews.llvm.org/D39386

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346512 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 16:36:24 +00:00
Krzysztof Parzyszek e21049990a [if-converter] Handle BBs that terminate in ret during diamond conversion
This fixes https://llvm.org/PR36825.

Original patch by Valentin Churavy (D45218).

Differential Revision: https://reviews.llvm.org/D45731


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330345 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-19 17:26:46 +00:00
Puyan Lotfi 1076969bfe Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323922 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-31 22:04:26 +00:00
Matthias Braun 66489736bf MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.
Specifying isSSA is an extra line at best and results in invalid MI at
worst. Compute the value instead.

Differential Revision: http://reviews.llvm.org/D22722

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279600 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24 01:32:41 +00:00
Matthias Braun 3346c15107 llc: Add support for -run-pass none
This does not schedule any passes besides the ones necessary to
construct and print the machine function. This is useful to test .mir
file reading and printing.

Differential Revision: http://reviews.llvm.org/D22432

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275664 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-16 02:24:59 +00:00
Quentin Colombet 3d35f0d482 [MIR] Print on the given output instead of stderr.
Currently the MIR framework prints all its outputs (errors and actual
representation) on stderr.

This patch fixes that by printing the regular output in the output
specified with -o.

Differential Revision: http://reviews.llvm.org/D22251

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275314 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-13 20:36:03 +00:00
Justin Lebar 3a1cea0888 When printing MIR, output to errs() rather than outs().
Summary:
Without this, this command

  $ llvm-run llc -stop-after machine-cp -o - <( echo '' )

outputs an error, because we close stdout twice -- once when closing the
file opened for "-o", and again when closing outs().

Also clarify in the outs() definition that you can't ever call it if you
want to open your own raw_fd_ostream on stdout.

Reviewers: jroelofs, tstellarAMD

Subscribers: jholewinski, qcolombet, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D17422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261286 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-19 00:18:46 +00:00
Alex Lorenz eecbba2d64 Fix PR 24724 - The implicit register verifier shouldn't assume certain operand
order.

The implicit register verifier in the MIR parser should only check if the
instruction's default implicit operands are present in the instruction. It
should not check the order in which they occur.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247283 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 14:04:34 +00:00