5 Commits

Author SHA1 Message Date
Nemanja Ivanovic 4a0e8977ca [PowerPC] Turn on CR-Logical reducer pass
This re-commits r375152 which was pulled in r375233 because it broke
the EXPENSIVE_CHECKS bot on Windows.

The reason for the failure was a bug in the pass that the commit turned
on by default. This patch fixes that bug and turns the pass back on.
This patch has been verified on the buildbot that originally failed
thanks to Simon Pilgrim.

Differential revision: https://reviews.llvm.org/D52431


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375497 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-22 12:20:38 +00:00
Nemanja Ivanovic 6ad9a8a867 Revert r375152 as it is causing failures on EXPENSIVE_CHECKS bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375233 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 13:38:46 +00:00
Nemanja Ivanovic 3c336dad2a [PowerPC] Turn on CR-Logical reducer pass
Quite a while ago, we implemented a pass that will reduce the number of
CR-logical operations we emit. It does so by converting a CR-logical operation
into a branch. We have kept this off by default because it seemed to cause a
significant regression with one benchmark.
However, that regression turned out to be due to a completely unrelated
reason - AADB introducing a self-copy that is a priority-setting nop and it was
just exacerbated by this pass.

Now that we understand the reason for the only degradation, we can turn this
pass on by default. We have long since fixed the cause for the degradation.

Differential revision: https://reviews.llvm.org/D52431


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375152 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-17 18:24:28 +00:00
Li Jia He 91a115149c [PowerPC] Fix a conversion is not considered when the ISD::BR_CC node making the instruction selection
Summary:
 A signed comparison of i1 values produces the opposite result to an unsigned one if the condition code 
 includes less-than or greater-than. This is so because 1 is the most negative signed i1 number and the 
 most positive unsigned i1 number. The CR-logical operations used for such comparisons are non-commutative
 so for signed comparisons vs. unsigned ones, the input operands just need to be swapped.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D54825


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347831 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-29 03:04:39 +00:00
Li Jia He be5fdae14b [PowerPC] [NFC] Add test cases to the ISD::BR_CC node in the instruction selection
Add the following test case for the ISD::BR_CC node in the instruction selection
define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
entry:
  %cmp1 = icmp eq i64 %c3, %c4
  %cmp3tmp = icmp eq i64 %c1, %c2
  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
  br i1 %cmp3, label %iftrue, label %iffalse
iftrue:
  ret i64 %a1
iffalse:
  ret i64 %a2
}
The data type i64 can be replaced by i32, i64, float, double

And condition codes can be replaced by: SETEQ, SETEN, SELT, SETLE, SETGT, SETGE,SETULT, SETULE, SSETGT, and SETUGE

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D54824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347828 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-29 02:51:03 +00:00