2 Commits

Author SHA1 Message Date
Roland Froese 0783d48fed [PowerPC] Avoid scalarization of vector truncate
The PowerPC code generator currently scalarizes vector truncates that would fit in a vector register, resulting in vector extracts, scalar operations, and vector merges. This patch custom lowers a vector truncate that would fit in a register to a vector shuffle instead.

Differential Revision: https://reviews.llvm.org/D56507


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353724 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-11 17:29:14 +00:00
Roland Froese e50fd44ed0 [PowerPC] Add vector truncate test to prep for D56507 NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353344 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-06 21:34:44 +00:00