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10 Commits

Author SHA1 Message Date
Luis Marques 1866c74977 [RISCV] Fix a couple of tests' CHECKs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370466 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-08-30 12:11:47 +00:00
Lewis Revill ef3be42de9 [RISCV] Lower inline asm constraint A for RISC-V 
This allows arguments with the constraint A to be lowered to input nodes
for RISC-V, which implies a memory address stored in a register.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

https://reviews.llvm.org/D54296



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369095 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-08-16 10:28:34 +00:00
Alex Bradbury 06c0e81ca5 [RISCV] Support z and i operand modifiers 
Differential Revision: https://reviews.llvm.org/D57792
Patch by James Clarke.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365291 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-07-08 05:00:26 +00:00
Alex Bradbury 5587c1846f [RISCV] Fix inline-asm.ll test by adding nounwind attribute 
This test failed since CFI directive support was added in r361320.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363123 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-12 05:32:30 +00:00
Lewis Revill 287b34ed8c [RISCV] Lower inline asm constraints I, J & K for RISC-V 
This validates and lowers arguments to inline asm nodes which have the
constraints I, J & K, with the following semantics (equivalent to GCC):

I: Any 12-bit signed immediate.
J: Immediate integer zero only.
K: Any 5-bit unsigned immediate.

Differential Revision: https://reviews.llvm.org/D54093



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363054 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-11 12:42:13 +00:00
Alex Bradbury 374b4f8d91 [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 
r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361493 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-05-23 12:43:13 +00:00
Alex Bradbury a568d027b0 [RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354028 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-02-14 13:09:54 +00:00
Alex Bradbury abb819e1e5 [RISCV] Peephole optimisation for load/store of global values or constant addresses 
(load (add base, off), 0) -> (load base, off)
(store val, (add base, off)) -> (store val, base, off)

This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327831 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-19 11:54:28 +00:00
Alex Bradbury ff5fe57525 [RISCV] Implement frame pointer elimination 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322839 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-01-18 11:34:02 +00:00
Alex Bradbury 077409ff7e [RISCV] Add basic support for inline asm constraints 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322217 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-01-10 20:05:09 +00:00