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Author SHA1 Message Date
Ulrich Weigand 43f4824b43 [SystemZ] Support vector registers in inline asm 
This adds support for specifying vector registers for use with inline
asm statements, either via the 'v' constraint or by explicit register
names (v0 ... v31).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326609 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 20:36:34 +00:00