8 Commits

Author SHA1 Message Date
Daniil Fukalov
8fbd41bc43 [AMDGPU] Inline asm - added i16, half and i128 types support
AMDGPU inline assembler support i16, half and i128 typed variables in constraints, but they were reported as error.
Needed to fix https://github.com/RadeonOpenCompute/ROCm/issues/341,
e.g. to be able to load with global_load_dwordx4 to a 128bit integer variable

Differential Revision: https://reviews.llvm.org/D44920

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334301 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-08 16:29:04 +00:00
Matt Arsenault
d706d030af AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
Currently the default C calling convention functions are treated
the same as compute kernels. Make this explicit so the default
calling convention can be changed to a non-kernel.

Converted with perl -pi -e 's/define void/define amdgpu_kernel void/'
on the relevant test directories (and undoing in one place that actually
wanted a non-kernel).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298444 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21 21:39:51 +00:00
Marek Olsak
2a24827c23 AMDGPU/SI: Add back reverted SGPR spilling code, but disable it
suggested as a better solution by Matt

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287942 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-25 17:37:09 +00:00
Marek Olsak
2acdc08776 Revert "AMDGPU: Make m0 unallocatable"
This reverts commit 124ad83dae04514f943902446520c859adee0e96.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287932 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-25 16:03:15 +00:00
Matt Arsenault
124ad83dae AMDGPU: Make m0 unallocatable
m0 may need to be written for spill code, so
we don't want general code uses relying on the
value stored in it.

This introduces a few code quality regressions where copies
from m0 are not coalesced into copies of a copy of m0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287841 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-24 00:26:40 +00:00
Matt Arsenault
e9a23c4c57 AMDGPU: Default to using scalar mov to materialize immediate
This is the conservatively correct way because it's easy to
move or replace a scalar immediate. This was incorrect in the case
when the register class wasn't known from the static instruction
definition, but still needed to be an SGPR. The main example of this
is inlineasm has an SGPR constraint.

Also start verifying the register classes of inlineasm operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285762 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01 22:55:07 +00:00
Matt Arsenault
605a81a85c AMDGPU: Relax SGPR asm constraint register class
s should be SReg_32 to be as general as possible. This can avoid a copy
from m0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280154 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-30 20:50:08 +00:00
Tom Stellard
6052acda66 AMDGPU/SI: Add support for sgpr and vgpr inline assembly constraints
Summary: The 's' constraint represents sgprs and the 'v' constraint represents vgprs.

Reviewers: arsenm, echristo

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15342

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255203 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-10 02:12:53 +00:00