10 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
3459520e80 [Hexagon] Update more testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326830 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 19:15:58 +00:00
Krzysztof Parzyszek
7f4371b614 [Hexagon] Replace instruction definitions with auto-generated ones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294753 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek
8ff1935865 [Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277626 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-03 18:35:48 +00:00
Krzysztof Parzyszek
9bad2f04b3 [Hexagon] Split double registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250549 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-16 20:38:54 +00:00
David Blaikie
7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00
Sirish Pande
0031af6615 Enable all Hexagon tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15 16:13:12 +00:00
Sirish Pande
2f69e4cf32 Disable Hexagon test temporarily.
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.

The assert is as follows:
    assert(!MI->isTerminator() && !MI->isLabel() &&
               "Cannot schedule terminators or labels!");

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12 21:06:54 +00:00
Benjamin Kramer
903456245b Hexagon: Fix a nasty order-of-initialization bug.
Reenable the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 19:08:59 +00:00
Tony Linthicum
781907b2b8 Temporarily disable Hexagon tests. They are failing on OS X
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 00:33:45 +00:00
Tony Linthicum
b4b54153ad Hexagon backend support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 21:14:40 +00:00