5 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
ccf5909298 [Hexagon] Reorganize and update instruction patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316228 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20 19:33:12 +00:00
Matt Arsenault
bdbe8280f2 Add address space mangling to lifetime intrinsics
In preparation for allowing allocas to have non-0 addrspace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299876 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 20:18:21 +00:00
Krzysztof Parzyszek
7f4371b614 [Hexagon] Replace instruction definitions with auto-generated ones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294753 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-10 15:33:13 +00:00
James Molloy
bd7c3fb3bf [LSR] Don't try and create post-inc expressions on non-rotated loops
If a loop is not rotated (for example when optimizing for size), the latch is not the backedge. If we promote an expression to post-inc form, we not only increase register pressure and add a COPY for that IV expression but for all IVs!

Motivating testcase:

    void f(float *a, float *b, float *c, int n) {
      while (n-- > 0)
        *c++ = *a++ + *b++;
    }

It's imperative that the pointer increments be located in the latch block and not the header block; if not, we cannot use post-increment loads and stores and we have to keep both the post-inc and pre-inc values around until the end of the latch which bloats register usage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278658 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-15 07:53:03 +00:00
Brendon Cahoon
a036cd4093 [Hexagon] Generate loop1 instruction for nested loops
loop1 is for the outer loop and loop0 is for the inner loop.

Differential Revision: http://reviews.llvm.org/D9680


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237266 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-13 17:56:03 +00:00