Summary: This is a NFC in preparation of exporting the initial registers as part of the YAML dump
Reviewers: courbet
Reviewed By: courbet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342967 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
This is a step towards fixing PR38048.
Note that right now the measurements are given per instruction. We'll
need to give measurements a per code snippet and update the analysis (PR38731).
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342947 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
The snippet-generation part goes to the SnippetGenerator class.
This will allow benchmarking arbitrary code (see PR38437).
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D51979
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342117 91177308-0d34-0410-b5e6-96231b3b80d8
Currently the cycle counter is taken from the subtarget schedule model, which
isn't any use if the subtarget doesn't have one. Delegate the decision to the
target benchmark runner, as it may know better what to do in that case, with
the default being the current behaviour.
Differential Revision: https://reviews.llvm.org/D48779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336099 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
This allows targets to override code generation for some instructions.
As an example of override, this also moves ad-hoc instruction filtering
for X86 into the X86 ExegesisTarget.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335582 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
On hover, the whole asm snippet is displayed, including operands.
This requires the actual assembly output instead of just the MCInsts:
This is because some pseudo-instructions get lowered to actual target
instructions during codegen (e.g. ABS_Fp32 -> SSE or X87).
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334805 91177308-0d34-0410-b5e6-96231b3b80d8
This breaks the OpenFlags enumeration into two separate
enumerations: OpenFlags and CreationDisposition. The first
controls the behavior of the API depending on whether or not
the target file already exists, and is not a flags-based
enum. The second controls more flags-like values.
This yields a more easy to understand API, while also allowing
flags to be passed to the openForRead api, where most of the
values didn't make sense before. This also makes the apis more
testable as it becomes easy to enumerate all the configurations
which make sense, so I've added many new tests to exercise all
the different values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334221 91177308-0d34-0410-b5e6-96231b3b80d8
We want llvm-exegesis to explore instructions (effect of initial register values, effect of operand selection). To enable this a BenchmarkResult muststore all the relevant data in its key. This patch starts adding such data. Here we simply allow to store the generated instructions, following patches will add operands and initial values for registers.
https://reviews.llvm.org/D47764
Authored by: Guilluame Chatelet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334008 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
Warn on instructions that should have the same performance
characteristics according to the sched model but actually
differ in their benchmarks.
Next step: Make the display nicer to browse, I was thinking maybe html.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D46945
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332601 91177308-0d34-0410-b5e6-96231b3b80d8
Restructuring the code to measure latency and uops.
The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash).
It now uses BitVector instead of Graph for performance reasons.
https://reviews.llvm.org/D46821
(with fixed ARM tests)
Authored by Guillaume Chatelet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332592 91177308-0d34-0410-b5e6-96231b3b80d8
Restructuring the code to measure latency and uops.
The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash).
It now uses BitVector instead of Graph for performance reasons.
https://reviews.llvm.org/D46821
Authored by Guillaume Chatelet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332579 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
The analysis mode gives the user a clustered view of the measurement results.
Next steps are (requires the split ok AsmTemplate.Name into {mnemonic, mode}):
- Show the sched class.
- Highlight any inconsistencies with the checked-in data.
Reviewers: gchatelet
Subscribers: mgorny, llvm-commits, tschuett
Differential Revision: https://reviews.llvm.org/D46865
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332344 91177308-0d34-0410-b5e6-96231b3b80d8
The analysis mode gives the user a clustered view of the measurement results and
highlights any inconsistencies with the checked-in data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332229 91177308-0d34-0410-b5e6-96231b3b80d8
We were calling getExtraProcessorInfo() without checking hasExtraProcessorInfo(), resulting in an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330263 91177308-0d34-0410-b5e6-96231b3b80d8
