299 Commits

Author SHA1 Message Date
Rafael Espindola
d980ed0d00 Move shouldAssumeDSOLocal to Target.
Should fix the shared library build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273958 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27 23:15:57 +00:00
Diana Picus
e50b5c5180 [ARM] Use member initializers in ARMSubtarget. NFCI
Same as r273556, but with C++11 member initializers.

Change suggested by Matthias Braun (see http://reviews.llvm.org/D21432).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273873 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27 13:06:10 +00:00
Diana Picus
92eaa569c3 [ARM] Do not test for CPUs, use SubtargetFeatures (Part 2). NFCI
This is a follow-up for r273544.

The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods.

Since the ARM backend seems to have quite a lot of calls to these methods, I
intend to submit 5-6 subtarget features at a time, instead of one big lump.

Differential Revision: http://reviews.llvm.org/D21685

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273853 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27 09:08:23 +00:00
Diana Picus
b0b7bd4d1e [ARM] Use member initializers in ARMSubtarget. NFCI
Move most of the initializations in ARMSubtarget::initializeEnvironment to
member initializers.

Change suggested by Matthias Braun (see http://reviews.llvm.org/D21432).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273556 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-23 12:04:33 +00:00
Diana Picus
f8f2c7f04e [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCI
This is a cleanup commit similar to r271555, but for ARM.

The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods.

Since the ARM backend seems to have quite a lot of calls to these methods, I
intend to submit 5-6 subtarget features at a time, instead of one big lump.

Differential Revision: http://reviews.llvm.org/D21432

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273544 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-23 07:47:35 +00:00
Sjoerd Meijer
2fca6568ee RAS extensions are part of ARMv8.2-A. This change enables them by introducing a
new instruction to ARM and AArch64 targets and several system registers.

Patch by: Roger Ferrer Ibanez and Oliver Stannard

Differential Revision: http://reviews.llvm.org/D20282


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271670 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-03 14:03:27 +00:00
Rafael Espindola
3d3b6e3e28 Start using shouldAssumeDSOLocal on ARM.
Given where this is used it should be a nop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271066 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-27 22:41:51 +00:00
Tim Northover
8362c240ca ARMv7k: base ABI decision on v7k Arch rather than watchos OS.
Various bits we want to use the new ABI actually compile with "-arch armv7k
-miphoneos-version-min=9.0". Not ideal, but also not ridiculous given how
slices work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258975 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-27 19:32:29 +00:00
Bradley Smith
aca9dcc971 [ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/Mainline
This patch was originally committed as r257883, but was reverted due to windows
failures. The cause of these failures has been fixed under r258677, hence
re-committing the original patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258681 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-25 11:24:47 +00:00
Reid Kleckner
30b888ab0e Revert "[ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/Mainline"
This reverts commit r257883.

Somehow this didn't make it into r257916.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257919 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-15 18:55:12 +00:00
Bradley Smith
bcfe6aa735 [ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/Mainline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257883 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-15 10:27:14 +00:00
Bradley Smith
002a07ce70 [ARM] Add ARMv8-A semaphore/atomic instructions to ARMv8-M Baseline/Mainline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257882 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-15 10:26:51 +00:00
Bradley Smith
eab7e23bdd [ARM] Add B.W and CBZ instructions to ARMv8-M Baseline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257881 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-15 10:26:17 +00:00
Bradley Smith
b7fd90158b [ARM] Add MOVW/MOVT instructions to ARMv8-M Baseline/Mainline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257879 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-15 10:25:14 +00:00
Bradley Smith
0283decdee [ARM] Add ARMv8-M Baseline/Mainline LLVM targeting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257878 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-15 10:24:39 +00:00
Bradley Smith
355f698c42 [ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate features
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257877 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-15 10:23:46 +00:00
Oliver Stannard
f025ca33c1 [ARM] Add subtarget features for ARMv8.2-A
This adds subtarget features for ARMv8.2-A, which builds on (and
requires the features from) ARMv8.1-A. Most assembler-visible features
of ARMv8.2-A are system instructions, and are all required parts of the
architecture, so just depend on the HasV8_2aOps subtarget feature.
There is also one large, optional feature, which adds 16-bit floating
point versions of all existing floating-point instructions (VFP and
SIMD), this is represented by the FeatureFullFP16 subtarget feature.

Differential Revision: http://reviews.llvm.org/D15036



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2015-12-01 10:23:06 +00:00
Tim Northover
c931f35508 ARM: make sure backend is consistent about exception handling method.
It turns out we decide whether to use SjLj exceptions or some alternative in
two separate places in the backend, and they disagreed with each other. This
led to inconsistent code and is generally a terrible idea.

So make them consistent and add an assert that they *do* match (unfortunately
MCAsmInfo isn't available in opt, so it can't be used to initialise the CodeGen
version directly).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253502 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-18 21:10:39 +00:00
Bradley Smith
50827137f2 [ARM] Default to ARMv4t in favour of adding Other to ARMArch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253335 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 13:38:29 +00:00
Bradley Smith
38bd0daf4d [ARM] Properly initialize ARMArch in the ARM subtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253331 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-17 11:57:33 +00:00
Tim Northover
ed754ee4a7 ARM: add support for WatchOS's compact unwind information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251573 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-28 22:56:36 +00:00
Tim Northover
7b7ff9e152 ARM: teach backend about WatchOS and TvOS libcalls.
The most substantial changes are again for watchOS: libcalls are hard-float if
needed and sincos has a different calling convention.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251571 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-28 22:51:16 +00:00
Tim Northover
26541ec6e9 ARM: add backend support for the ABI used in WatchOS
At the LLVM level this ABI is essentially a minimal modification of AAPCS to
support 16-byte alignment for vector types and the stack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251570 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-28 22:46:43 +00:00
Artyom Skrobov
c0ae278730 [ARM] Avoid redundant checks for isThumb1Only() after supportsTailCall()
supportsTailCall() has two callers. Both of them double-check isThumb1Only(),
and refuse to proceed with tail-calling in that case.
Therefore, it makes sense to move this check to
ARMSubtarget::initSubtargetFeatures, where SupportsTailCall is initialized;
and to eliminate the extra checks at the call sites.

Following a review comment, added an "assert(supportsTailCall())"
in IsEligibleForTailCall.

NFC.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248703 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-28 09:44:11 +00:00
Artyom Skrobov
c848236c93 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a
hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with
a FIXME: attached.

This patch changes the handling of +t2dsp to be in line with other
architecture extensions.

Following a revert of r248152 and new review comments, this patch also includes
renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc.
The spelling of "t2dsp" is preserved, pending a further investigation of its
possible external usage.

Differential Revision: http://reviews.llvm.org/D12937



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248519 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 17:31:16 +00:00
Oliver Stannard
425f047fd1 [ARM] Add option to force fast-isel
The ARM backend has some logic that only allows the fast-isel to be enabled for
subtargets where it is known to be stable. This adds a backend option to
override this and force the fast-isel to be used for any target, to allow it to
be tested.

This is an ARM-specific option, because no other backend disables the fast-isel
on a per-subtarget basis.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248369 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-23 09:19:54 +00:00
Eric Christopher
c4db514911 Limit the range of processors supported by ARM fast isel to v6 or
later as that's all that is tested right now.

Fixes PR24858.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248027 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-18 20:08:18 +00:00
Daniel Sanders
47b167dd84 Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Eric has replied and has demanded the patch be reverted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247702 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 16:17:27 +00:00
Daniel Sanders
9781f90c7e Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Summary:
This is the first patch in the series to migrate Triple's (which are ambiguous)
to TargetTuple's (which aren't).

For the moment, TargetTuple simply passes all requests to the Triple object it
holds. Once it has replaced Triple, it will start to implement the interface in
a more suitable way.

This change makes some changes to the public C++ API. In particular,
InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer()
now take TargetTuples instead of Triples. The other public C++ API's have
been left as-is for the moment to reduce patch size.

This commit also contains a trivial patch to clang to account for the C++ API
change. Thanks go to Pavel Labath for fixing LLDB for me.

Reviewers: rengolin

Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10969


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247692 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 14:08:28 +00:00
Daniel Sanders
a6aa0c3bcc Revert r247684 - Replace Triple with a new TargetTuple ...
LLDB needs to be updated in the same commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247686 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 13:46:21 +00:00
Daniel Sanders
7b82808e13 Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Summary:
This is the first patch in the series to migrate Triple's (which are ambiguous)
to TargetTuple's (which aren't).

For the moment, TargetTuple simply passes all requests to the Triple object it
holds. Once it has replaced Triple, it will start to implement the interface in
a more suitable way.

This change makes some changes to the public C++ API. In particular,
InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer()
now take TargetTuples instead of Triples. The other public C++ API's have
been left as-is for the moment to reduce patch size.

This commit also contains a trivial patch to clang to account for the C++ API
change.

Reviewers: rengolin

Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10969



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247683 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 13:17:40 +00:00
Sanjay Patel
08c1ad0c38 use minSize wrapper; NFCI
These were missed when other uses were switched over:
http://llvm.org/viewvc/llvm-project?view=revision&revision=243994



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245311 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-18 16:44:23 +00:00
Sanjay Patel
f360983642 wrap OptSize and MinSize attributes for easier and consistent access (NFCI)
Create wrapper methods in the Function class for the OptimizeForSize and MinSize
attributes. We want to hide the logic of "or'ing" them together when optimizing
just for size (-Os).

Currently, we are not consistent about this and rely on a front-end to always set
OptimizeForSize (-Os) if MinSize (-Oz) is on. Thus, there are 18 FIXME changes here
that should be added as follow-on patches with regression tests.

This patch is NFC-intended: it just replaces existing direct accesses of the attributes
by the equivalent wrapper call.

Differential Revision: http://reviews.llvm.org/D11734



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243994 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-04 15:49:57 +00:00
Tim Northover
5647cdb099 ARM: remove horrible printf left over from debugging
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243907 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-03 22:19:08 +00:00
Tim Northover
8927f6cd0f ARM: prefer allocating VFP regs at stride 4 on Darwin.
This is necessary for WatchOS support, where the compact unwind format assumes
this kind of layout. For now we only want this on Swift-like CPUs though, where
it's been the Xcode behaviour for ages. Also, since it can expand the prologue
we don't want it at -Oz.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243884 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-03 17:20:10 +00:00
Akira Hatanaka
4fb2f3310a [ARM] Define subtarget feature strict-align.
This commit defines subtarget feature strict-align and uses it instead of
cl::opt -arm-strict-align to decide whether strict alignment should be
forced. Also, remove the logic that was checking the OS and architecture
as clang is now responsible for setting strict-align based on the command
line options specified and the target architecute and OS.

rdar://problem/21529937

http://reviews.llvm.org/D11470

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243493 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 22:44:28 +00:00
Akira Hatanaka
27ac0fae47 [ARM] Define subtarget feature "reserve-r9", which is used to decide
whether register r9 should be reserved.

This recommits r242737, which broke bots because the number of subtarget
features went over the limit of 64.

This change is needed because we cannot use a backend option to set
cl::opt "arm-reserve-r9" when doing LTO.

Out-of-tree projects currently using cl::opt option "-arm-reserve-r9" to
reserve r9 should make changes to add subtarget feature "reserve-r9" to
the IR.

rdar://problem/21529937

Differential Revision: http://reviews.llvm.org/D11320


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242756 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-21 01:42:02 +00:00
Akira Hatanaka
4f50f9eba4 Revert r242737.
This caused builds to fail with the following error message:

error:Too many subtarget features! Bump MAX_SUBTARGET_FEATURES.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242740 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20 23:51:12 +00:00
Akira Hatanaka
a22e4b71f4 [ARM] Define subtarget feature "reserve-r9", which is used to decide
whether register r9 should be reserved.

This change is needed because we cannot use a backend option to set
cl::opt "arm-reserve-r9" when doing LTO.

Out-of-tree projects currently using cl::opt option "-arm-reserve-r9" to
reserve r9 should make changes to add subtarget feature "reserve-r9" to
the IR.

rdar://problem/21529937

Differential Revision: http://reviews.llvm.org/D11320


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242737 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20 23:21:30 +00:00
Matthias Braun
6f6ca40ef0 ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
Reapply r242500 now that the swift schedmodel includes LDRLIT.

This is mostly done to disable the PostRAScheduler which optimizes for
instruction latencies which isn't a good fit for out-of-order
architectures. This also allows to leave out the itinerary table in
swift in favor of the SchedModel ones.

This change leads to performance improvements/regressions by as much as
10% in some benchmarks, in fact we loose 0.4% performance over the
llvm-testsuite for reasons that appear to be unknown or out of the
compilers control. rdar://20803802 documents the investigation of
these effects.

While it is probably a good idea to perform the same switch for the
other ARM out-of-order CPUs, I limited this change to swift as I cannot
perform the benchmark verification on the other CPUs.

Differential Revision: http://reviews.llvm.org/D10513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242588 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-17 23:18:30 +00:00
Adam Nemet
fadee632e1 Revert "ARM: Enable MachineScheduler and disable PostRAScheduler for swift."
This reverts commit r242500.

It broke some internal tests and Matthias asked me to revert it while he
is investigating.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242553 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-17 18:14:19 +00:00
Matthias Braun
c8fe2bf3a4 ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
This is mostly done to disable the PostRAScheduler which optimizes for
instruction latencies which isn't a good fit for out-of-order
architectures. This also allows to leave out the itinerary table in
swift in favor of the SchedModel ones.

This change leads to performance improvements/regressions by as much as
10% in some benchmarks, in fact we loose 0.4% performance over the
llvm-testsuite for reasons that appear to be unknown or out of the
compilers control. rdar://20803802 documents the investigation of
these effects.

While it is probably a good idea to perform the same switch for the
other ARM out-of-order CPUs, I limited this change to swift as I cannot
perform the benchmark verification on the other CPUs.

Differential Revision: http://reviews.llvm.org/D10513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242500 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-17 01:44:31 +00:00
Akira Hatanaka
6780493e8d [ARM] Define a subtarget feature that is used to avoid using movt/movw
pairs for 32-bit immediates.

This change is needed to avoid emitting movt/movw pairs when doing LTO
and do so on a per-function basis.

Out-of-tree projects currently using cl::opt option -arm-use-movt=0 or
false to avoid emitting movt/movw pairs should make changes to add
subtarget feature "+no-movt" (see the changes made to clang in r242368).

rdar://problem/21529937

Differential Revision: http://reviews.llvm.org/D11026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242369 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 00:58:23 +00:00
Mehdi Amini
dc4dccabf3 Remove getDataLayout() from TargetSelectionDAGInfo (had no users)
Summary:
Remove empty subclass in the process.

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren, ted

Differential Revision: http://reviews.llvm.org/D11045

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241780 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:10:08 +00:00
Akira Hatanaka
a744879a65 [ARM] Define a subtarget feature and use it to decide whether long calls should
be emitted.

This is needed to enable ARM long calls for LTO and enable and disable it on a
per-function basis.

Out-of-tree projects currently using EnableARMLongCalls to emit long calls
should start passing "+long-calls" to the feature string (see the changes made
to clang in r241565).

rdar://problem/21529937

Differential Revision: http://reviews.llvm.org/D9364


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241566 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-07 06:54:42 +00:00
Peter Collingbourne
ce2b45bd7d IR: Do not consider available_externally linkage to be linker-weak.
From the linker's perspective, an available_externally global is equivalent
to an external declaration (per isDeclarationForLinker()), so it is incorrect
to consider it to be a weak definition.

Also clean up some logic in the dead argument elimination pass and clarify
its comments to better explain how its behavior depends on linkage,
introduce GlobalValue::isStrongDefinitionForLinker() and start using
it throughout the optimizers and backend.

Differential Revision: http://reviews.llvm.org/D10941

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241413 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 20:52:35 +00:00
Matthias Braun
8ce6c58e41 Rename TargetSubtargetInfo::enablePostMachineScheduler() to enablePostRAScheduler()
r213101 changed the behaviour of this method to not only affect the
PostMachineScheduler scheduler but also the PostRAScheduler scheduler,
renaming should make this fact clear. Also document that the preferred
way is to specify this in the scheduling model instead of overriding
this method.

Differential Revision: http://reviews.llvm.org/D10427

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239659 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:42:16 +00:00
Daniel Sanders
4d13f315d1 Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC.
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rafael

Reviewed By: rafael

Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10311


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239467 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 12:11:26 +00:00
Michael Kuperstein
d714fcf5c8 Use std::bitset for SubtargetFeatures.
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures.
Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. 
This should now be fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238192 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-26 10:47:10 +00:00
Akira Hatanaka
01461204b3 Stop resetting NoFramePointerElim in TargetMachine::resetTargetOptions.
This is part of the work to remove TargetMachine::resetTargetOptions.

In this patch, instead of updating global variable NoFramePointerElim in
resetTargetOptions, its use in DisableFramePointerElim is replaced with a call
to TargetFrameLowering::noFramePointerElim. This function determines on a
per-function basis if frame pointer elimination should be disabled.

There is no change in functionality except that cl:opt option "disable-fp-elim"
can now override function attribute "no-frame-pointer-elim". 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238080 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-23 01:14:08 +00:00