Currently this test causes test failures on some machines, due to isel not being registered. Update the test to run all passes and check emitted assembly instructions for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311545 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: In some cases, shufflevector instruction can be transformed involving insert_subvector instructions. The ARM backend was missing some insert_subvector patterns, causing a failure during instruction selection. AArch64 has similar patterns.
Reviewers: t.p.northover, olista01, javed.absar, rengolin
Reviewed By: javed.absar
Subscribers: aemerson, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D36796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311543 91177308-0d34-0410-b5e6-96231b3b80d8
