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3 Commits

Author SHA1 Message Date
Simon Pilgrim
b648fac5ca [SelectionDAG] Add support for BITREVERSE constant folding 
We were relying on constant folding of the legalized instructions to do what constant folding we had previously

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292114 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-16 13:39:00 +00:00
James Molloy
b5ab3ba365 [ARM] Replace ARMISD::RBIT with ISD::BITREVERSE 
ISD::BITREVERSE matches "rbit" completely, so remove ARMISD::RBIT and mark ISD::BITREVERSE as legal, adding a test for lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253047 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-11-13 16:05:22 +00:00
Yi Kong
40f9d11ccc ARM: Fix codegen for rbit intrinsic 
LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic.
According to ARM ARM, rbit only takes register as argument, not immediate.
The correct instruction should be rbit <Rd>, <Rm>.

The bug was originally introduced in r211057.

Differential Revision: http://reviews.llvm.org/D4980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216064 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-20 10:40:20 +00:00