3 Commits

Author SHA1 Message Date
Nemanja Ivanovic
53979264b2 [DAGCombiner] Expand combining of FP logical ops to sign-setting FP ops
We already do the following combines:
(bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X
(bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X

When the target has "bit preserving fp logic". This patch just extends it
to also combine:
(bitcast int (or (bitcast fp X to int), 0x8000...) to fp) -> fneg (fabs X)

As some targets have fnabs and even those that don't can efficiently lower
both the fabs and the fneg.

Differential revision: https://reviews.llvm.org/D44548


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344093 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-09 23:20:11 +00:00
Nemanja Ivanovic
2e2e17dd9c [PowerPC][NFC] Commit nabs test case in preparation for committing D44548
This just adds the test case so that the different code gen is clearly visible
when the DAG Combine lands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344091 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-09 23:02:53 +00:00
Nemanja Ivanovic
7df2b65a85 [PowerPC] Implement hasBitPreservingFPLogic for types that can be supported
This is the PPC-specific non-controversial part of
https://reviews.llvm.org/D44548 that simply enables this combine for PPC
since PPC has these instructions.
This commit will allow the target-independent portion to be truly target
independent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344077 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-09 20:35:15 +00:00