2 Commits

Author SHA1 Message Date
Alex Bradbury
5816be49d6 [RISCV] Add RV64F codegen support
This requires a little extra work due tothe fact i32 is not a legal type. When
call lowering happens post-legalisation (e.g. when an intrinsic was inserted
during legalisation). A bitcast from f32 to i32 can't be introduced. This is
similar to the challenges with RV32D. To handle this, we introduce
target-specific DAG nodes that perform bitcast+anyext for f32->i64 and
trunc+bitcast for i64->f32.

Differential Revision: https://reviews.llvm.org/D53235



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352807 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-31 22:48:38 +00:00
Alex Bradbury
8ce26eb802 [RISCV] Add codegen for RV32F floating point load/store
As part of this, add support for load/store from the constant pool. This is
used to materialise f32 constants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327979 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-20 13:26:12 +00:00